ARM: dts: mvebu: pl310-cache disable double-linefill
authorYan Markman <ymarkman@marvell.com>
Sat, 15 Oct 2016 21:22:32 +0000 (00:22 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 8 Nov 2017 09:06:27 +0000 (10:06 +0100)
commit cda80a82ac3e89309706c027ada6ab232be1d640 upstream.

Under heavy system stress mvebu SoC using Cortex A9 sporadically
encountered instability issues.

The "double linefill" feature of L2 cache was identified as causing
dependency between read and write which lead to the deadlock.

Especially, it was the cause of deadlock seen under heavy PCIe traffic,
as this dependency violates PCIE overtaking rule.

Fixes: c8f5a878e554 ("ARM: mvebu: use DT properties to fine-tune the L2 configuration")
Signed-off-by: Yan Markman <ymarkman@marvell.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
[gregory.clement@free-electrons.com: reformulate commit log, add Armada
375 and add Fixes tag]
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/arm/boot/dts/armada-375.dtsi
arch/arm/boot/dts/armada-38x.dtsi
arch/arm/boot/dts/armada-39x.dtsi

index cc952cf8ec3003b6339629161b40e2410ece51d4..024f1b75b0a347e270d3a5b86c834acf179a5805 100644 (file)
                                reg = <0x8000 0x1000>;
                                cache-unified;
                                cache-level = <2>;
-                               arm,double-linefill-incr = <1>;
+                               arm,double-linefill-incr = <0>;
                                arm,double-linefill-wrap = <0>;
-                               arm,double-linefill = <1>;
+                               arm,double-linefill = <0>;
                                prefetch-data = <1>;
                        };
 
index e8b7f67267723241730c8279902b82b8340d8118..bf20918f1fad94cc6ec67b4d143339407243f0a5 100644 (file)
                                reg = <0x8000 0x1000>;
                                cache-unified;
                                cache-level = <2>;
-                               arm,double-linefill-incr = <1>;
+                               arm,double-linefill-incr = <0>;
                                arm,double-linefill-wrap = <0>;
-                               arm,double-linefill = <1>;
+                               arm,double-linefill = <0>;
                                prefetch-data = <1>;
                        };
 
index dc6efd386dbcb00db09c5e8171f15f83beb1dd09..e67f1fd7a4d1c3a4d979690d3fd55bd0025ab601 100644 (file)
                                reg = <0x8000 0x1000>;
                                cache-unified;
                                cache-level = <2>;
-                               arm,double-linefill-incr = <1>;
+                               arm,double-linefill-incr = <0>;
                                arm,double-linefill-wrap = <0>;
-                               arm,double-linefill = <1>;
+                               arm,double-linefill = <0>;
                                prefetch-data = <1>;
                        };