drm/i915/cnl: Setup PAT Index.

Different from previous platforms, on CNL+ there's separated
registers for separated indexes.

v2: Remove comments regarding uncertainty around the table.
v3: Remove extra line (by Ben)

Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170815232539.3562-1-rodrigo.vivi@intel.com

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ef1881e256f4971acc4e9bbb1c4eb4851023c62a..d60f38adc4c43aa49b1db183d2c859bf565d8c4b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2742,6 +2742,24 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
        return 0;
 }
 
+static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
+{
+       /* XXX: spec is unclear if this is still needed for CNL+ */
+       if (!USES_PPGTT(dev_priv)) {
+               I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC);
+               return;
+       }
+
+       I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC);
+       I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
+       I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
+       I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC);
+       I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
+       I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
+       I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
+       I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+}
+
 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
  * bits. When using advanced contexts each context stores its own PAT, but
  * writing this data shouldn't be harmful even in those cases. */
@@ -2856,7 +2874,9 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
        ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
 
-       if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
+       if (INTEL_GEN(dev_priv) >= 10)
+               cnl_setup_private_ppat(dev_priv);
+       else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
                chv_setup_private_ppat(dev_priv);
        else
                bdw_setup_private_ppat(dev_priv);
@@ -3138,7 +3158,9 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
        ggtt->base.closed = false;
 
        if (INTEL_GEN(dev_priv) >= 8) {
-               if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
+               if (INTEL_GEN(dev_priv) >= 10)
+                       cnl_setup_private_ppat(dev_priv);
+               else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
                        chv_setup_private_ppat(dev_priv);
                else
                        bdw_setup_private_ppat(dev_priv);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b2d785969d17f121c6083c0226707f14b8862bba..ed7cd9ee2c2af89737b2cc4618317c4d2fc9bedd 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2336,6 +2336,7 @@ enum i915_power_well_id {
 #define DONE_REG               _MMIO(0x40b0)
 #define GEN8_PRIVATE_PAT_LO    _MMIO(0x40e0)
 #define GEN8_PRIVATE_PAT_HI    _MMIO(0x40e0 + 4)
+#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + index*4)
 #define BSD_HWS_PGA_GEN7       _MMIO(0x04180)
 #define BLT_HWS_PGA_GEN7       _MMIO(0x04280)
 #define VEBOX_HWS_PGA_GEN7     _MMIO(0x04380)