}
else if (mali_pp_scale_threshold[MALI_PP_THRESHOLD_40]< data->utilization_pp)
{
+ #if 0
currentStep = MALI_CLOCK_425;
schedule_work(&wq_work);
+ #endif
}
else if (0 < data->utilization_pp)
{
+ #if 0
if (num_cores_enabled == 1) {
if ( mali_pp_scale_threshold[MALI_PP_THRESHOLD_30]< data->utilization_pp )
currentStep = MALI_CLOCK_318;
} else {
disable_one_core();
}
+ #else
+ disable_one_core();
+ #endif
}
else
{
u32 utilization = data->utilization_gpu;
if (utilization > mali_dvfs_threshold[currentStep].upthreshold) {
+ #if 0
if (utilization < mali_utilization_high && currentStep < MALI_CLOCK_INDX_MAX)
currentStep ++;
else
+ #endif
currentStep = MALI_CLOCK_637;
- if (data->utilization_pp > MALI_PP_THRESHOLD_90) // 90%
+ if (data->utilization_pp > MALI_PP_THRESHOLD_90) { // 90%
enable_max_num_cores();
- else
+ } else {
enable_one_core();
- } else if (utilization < mali_dvfs_threshold[currentStep].downthreshold && currentStep > 0) {
+ }
+ } else if (utilization < mali_dvfs_threshold[currentStep].downthreshold && currentStep > 1) {
currentStep--;
MALI_DEBUG_PRINT(2, ("Mali clock set %d..\n",currentStep));
} else {
MALI_SCALING_MODE_MAX
};
-static int scaling_mode = MALI_PP_SCALING;
+static int scaling_mode = MALI_PP_FS_SCALING;
module_param(scaling_mode, int, 0664);
MODULE_PARM_DESC(scaling_mode, "0 disable, 1 pp, 2 fs, 4 double");
static int last_scaling_mode;
.fb_start = 0x84000000,
#endif
.fb_size = 0x06000000,
- .utilization_interval = 1000,
+ .utilization_interval = 500,
.utilization_callback = mali_gpu_utilization_callback,
.pmu_switch_delay = 0xFFFF, /* do not have to be this high on FPGA, but it is good for testing to have a delay */
};