drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6

Move call to gen9_set_dc_state_debugmask_memory_up() into
gen9_set_dc_state() to prevent us missing it somewhere.

Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447084107-8521-3-git-send-email-patrik.jakobsson@linux.intel.com

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index cf36b86154158f49d927e54c714388d32bbd7cce..d31a934e525cb527c4e0c36a391bd4b90abb5971 100644 (file)
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -395,6 +395,20 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
          */
 }
 
+static void gen9_set_dc_state_debugmask_memory_up(
+                       struct drm_i915_private *dev_priv)
+{
+       uint32_t val;
+
+       /* The below bit doesn't need to be cleared ever afterwards */
+       val = I915_READ(DC_STATE_DEBUG);
+       if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
+               val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
+               I915_WRITE(DC_STATE_DEBUG, val);
+               POSTING_READ(DC_STATE_DEBUG);
+       }
+}
+
 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 {
        uint32_t val;
@@ -408,6 +422,9 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 
        WARN_ON_ONCE(state & ~mask);
 
+       if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
+               gen9_set_dc_state_debugmask_memory_up(dev_priv);
+
        val = I915_READ(DC_STATE_EN);
        DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
                      val & mask, state);
@@ -435,20 +452,6 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv)
        gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 }
 
-static void gen9_set_dc_state_debugmask_memory_up(
-                       struct drm_i915_private *dev_priv)
-{
-       uint32_t val;
-
-       /* The below bit doesn't need to be cleared ever afterwards */
-       val = I915_READ(DC_STATE_DEBUG);
-       if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
-               val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
-               I915_WRITE(DC_STATE_DEBUG, val);
-               POSTING_READ(DC_STATE_DEBUG);
-       }
-}
-
 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 {
        WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
@@ -497,8 +500,6 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 
        DRM_DEBUG_KMS("Enabling DC5\n");
 
-       gen9_set_dc_state_debugmask_memory_up(dev_priv);
-
        gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 }
 
@@ -544,8 +545,6 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv)
 
        DRM_DEBUG_KMS("Enabling DC6\n");
 
-       gen9_set_dc_state_debugmask_memory_up(dev_priv);
-
        gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 
 }