mlx4_core: Add support for steerable IB UD QPs
authorMatan Barak <matanb@mellanox.com>
Thu, 7 Nov 2013 13:25:14 +0000 (15:25 +0200)
committerRoland Dreier <roland@purestorage.com>
Tue, 14 Jan 2014 22:06:50 +0000 (14:06 -0800)
This patch adds support for allocating IB UD QPs that we can steer
traffic from.  We introduce a new firmware command FLOW_STEERING_IB_UC_QP_RANGE
and a capability bit.

This command isn't supported for VFs.

Signed-off-by: Matan Barak <matanb@mellanox.com>
Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
drivers/net/ethernet/mellanox/mlx4/cmd.c
drivers/net/ethernet/mellanox/mlx4/fw.c
drivers/net/ethernet/mellanox/mlx4/mcg.c
drivers/net/ethernet/mellanox/mlx4/mlx4.h
drivers/net/ethernet/mellanox/mlx4/resource_tracker.c
include/linux/mlx4/cmd.h
include/linux/mlx4/device.h

index 1e9970d2f0f38c733ef100db4e91e762eb68da5e..0d02fba9453657588b5f3db7b2e90e7e5410b010 100644 (file)
@@ -1371,6 +1371,15 @@ static struct mlx4_cmd_info cmd_info[] = {
                .verify = NULL,
                .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
        },
+       {
+               .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
+               .has_inbox = false,
+               .has_outbox = false,
+               .out_is_imm = false,
+               .encode_slave_id = false,
+               .verify = NULL,
+               .wrapper = mlx4_FLOW_STEERING_IB_UC_QP_RANGE_wrapper
+       },
 };
 
 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
index 194928214606e160932fcb335f604421431b6eb2..4bd2d80d065e0555ae18d6c8795373912738b944 100644 (file)
@@ -513,6 +513,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 #define QUERY_DEV_CAP_MAX_XRC_OFFSET           0x67
 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET      0x68
 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET       0x70
+#define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET       0x74
 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET    0x76
 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET      0x77
 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET   0x80
@@ -603,6 +604,9 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
        if (field & 0x80)
                dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
        dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
+       MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
+       if (field & 0x80)
+               dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
        MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
        dev_cap->fs_max_num_qp_per_entry = field;
        MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
@@ -860,6 +864,12 @@ int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
                MLX4_PUT(outbox->buf, field,
                         QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
        }
+
+       /* turn off ipoib managed steering for guests */
+       MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
+       field &= ~0x80;
+       MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
+
        return 0;
 }
 
index acf9d5f1f9223fbfa0e4efa1b9d886186a12c0cf..34dffcf61bffb2114a82b7281e9c2e840a92dcac 100644 (file)
@@ -895,6 +895,23 @@ int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id)
 }
 EXPORT_SYMBOL_GPL(mlx4_flow_detach);
 
+int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
+                                     u32 max_range_qpn)
+{
+       int err;
+       u64 in_param;
+
+       in_param = ((u64) min_range_qpn) << 32;
+       in_param |= ((u64) max_range_qpn) & 0xFFFFFFFF;
+
+       err = mlx4_cmd(dev, in_param, 0, 0,
+                       MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
+                       MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
+
+       return err;
+}
+EXPORT_SYMBOL_GPL(mlx4_FLOW_STEERING_IB_UC_QP_RANGE);
+
 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
                          int block_mcast_loopback, enum mlx4_protocol prot,
                          enum mlx4_steer_type steer)
index e582a41a802baeddba0aa9c68dd79113a1cd236e..59f67f9086dc38567dbc0c1992a7c67245a0773e 100644 (file)
@@ -1236,6 +1236,11 @@ int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
                                         struct mlx4_cmd_mailbox *inbox,
                                         struct mlx4_cmd_mailbox *outbox,
                                         struct mlx4_cmd_info *cmd);
+int mlx4_FLOW_STEERING_IB_UC_QP_RANGE_wrapper(struct mlx4_dev *dev, int slave,
+                                             struct mlx4_vhcr *vhcr,
+                                             struct mlx4_cmd_mailbox *inbox,
+                                             struct mlx4_cmd_mailbox *outbox,
+                                             struct mlx4_cmd_info *cmd);
 
 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
index 2f3f2bc7f2837e2d7eef7c42ced3a2ffad8f0e56..663510325c22421cb8958f33238dc7ed7c60bd42 100644 (file)
@@ -3844,6 +3844,16 @@ int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
        return err;
 }
 
+int mlx4_FLOW_STEERING_IB_UC_QP_RANGE_wrapper(struct mlx4_dev *dev, int slave,
+                                             struct mlx4_vhcr *vhcr,
+                                             struct mlx4_cmd_mailbox *inbox,
+                                             struct mlx4_cmd_mailbox *outbox,
+                                             struct mlx4_cmd_info *cmd)
+{
+       return -EPERM;
+}
+
+
 static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
 {
        struct res_gid *rgid;
index 8df61bc5da00ff9d751727c42ee93b2c6ad7de9f..ff36620f88a70ef5c84f1a7f6e58fb519c0fb767 100644 (file)
@@ -157,6 +157,7 @@ enum {
        /* register/delete flow steering network rules */
        MLX4_QP_FLOW_STEERING_ATTACH = 0x65,
        MLX4_QP_FLOW_STEERING_DETACH = 0x66,
+       MLX4_FLOW_STEERING_IB_UC_QP_RANGE = 0x64,
 };
 
 enum {
index 7d3a523160ba4906aaa3c03290bcea20920c4b59..7de9fde3a9dd218421d91f45c7c5e4cba1b61f8f 100644 (file)
@@ -160,7 +160,8 @@ enum {
        MLX4_DEV_CAP_FLAG2_TS                   = 1LL <<  5,
        MLX4_DEV_CAP_FLAG2_VLAN_CONTROL         = 1LL <<  6,
        MLX4_DEV_CAP_FLAG2_FSM                  = 1LL <<  7,
-       MLX4_DEV_CAP_FLAG2_UPDATE_QP            = 1LL <<  8
+       MLX4_DEV_CAP_FLAG2_UPDATE_QP            = 1LL <<  8,
+       MLX4_DEV_CAP_FLAG2_DMFS_IPOIB           = 1LL <<  9
 };
 
 enum {
@@ -1144,6 +1145,9 @@ int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int
 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
 
+int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
+                                     u32 max_range_qpn);
+
 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
 
 #endif /* MLX4_DEVICE_H */