PCI: imx6: Factor out ref clock enable

Factor out ref clock enable to make it cleaner to add imx6sx support.  No
functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Christoph Fritz <chf.fritz@googlemail.com>

diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index 2f817fa4c661e72274e873c38f460cefe04faa79..4357f4d90d0cc7b43a29a428c761663f2736aca8 100644 (file)
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -269,6 +269,23 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
        return 0;
 }
 
+static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
+{
+       /* power up core phy and enable ref clock */
+       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+                       IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
+       /*
+        * the async reset input need ref clock to sync internally,
+        * when the ref clock comes after reset, internal synced
+        * reset time is too short, cannot meet the requirement.
+        * add one ~10us delay here.
+        */
+       udelay(10);
+       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+                       IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+       return 0;
+}
+
 static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 {
        struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
@@ -292,18 +309,11 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
                goto err_pcie;
        }
 
-       /* power up core phy and enable ref clock */
-       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-                       IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
-       /*
-        * the async reset input need ref clock to sync internally,
-        * when the ref clock comes after reset, internal synced
-        * reset time is too short, cannot meet the requirement.
-        * add one ~10us delay here.
-        */
-       udelay(10);
-       regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-                       IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+       ret = imx6_pcie_enable_ref_clk(imx6_pcie);
+       if (ret) {
+               dev_err(pp->dev, "unable to enable pcie ref clock\n");
+               goto err_ref_clk;
+       }
 
        /* allow the clocks to stabilize */
        usleep_range(200, 500);
@@ -316,6 +326,8 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
        }
        return 0;
 
+err_ref_clk:
+       clk_disable_unprepare(imx6_pcie->pcie);
 err_pcie:
        clk_disable_unprepare(imx6_pcie->pcie_bus);
 err_pcie_bus: