struct device_node *node, u32 feature, const char *compatible)
{
struct fsl_dma_chan *new_fsl_chan;
+ struct resource res;
int err;
/* alloc channel */
}
/* get dma channel register base */
- err = of_address_to_resource(node, 0, &new_fsl_chan->reg);
+ err = of_address_to_resource(node, 0, &res);
if (err) {
dev_err(fdev->dev, "Can't get %s property 'reg'\n",
node->full_name);
WARN_ON(fdev->feature != new_fsl_chan->feature);
new_fsl_chan->dev = fdev->dev;
- new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start,
- new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1);
-
- new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7;
+ new_fsl_chan->reg_base = ioremap(res.start, resource_size(&res));
+ new_fsl_chan->id = ((res.start - 0x100) & 0xfff) >> 7;
if (new_fsl_chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
dev_err(fdev->dev, "There is no %d channel!\n",
new_fsl_chan->id);
int err;
struct fsl_dma_device *fdev;
struct device_node *child;
+ struct resource res;
fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL);
if (!fdev) {
INIT_LIST_HEAD(&fdev->common.channels);
/* get DMA controller register base */
- err = of_address_to_resource(dev->node, 0, &fdev->reg);
+ err = of_address_to_resource(dev->node, 0, &res);
if (err) {
dev_err(&dev->dev, "Can't get %s property 'reg'\n",
dev->node->full_name);
dev_info(&dev->dev, "Probe the Freescale DMA driver for %s "
"controller at 0x%llx...\n",
- match->compatible, (unsigned long long)fdev->reg.start);
- fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end
- - fdev->reg.start + 1);
+ match->compatible, (unsigned long long)res.start);
+ fdev->reg_base = ioremap(res.start, resource_size(&res));
dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
struct list_head node;
struct list_head tx_list;
struct dma_async_tx_descriptor async_tx;
- struct list_head *ld;
- void *priv;
} __attribute__((aligned(32)));
struct fsl_dma_chan_regs {
struct fsl_dma_device {
void __iomem *reg_base; /* DGSR register base */
- struct resource reg; /* Resource for register */
struct device *dev;
struct dma_device common;
struct fsl_dma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
struct dma_chan common; /* DMA common channel */
struct dma_pool *desc_pool; /* Descriptors pool */
struct device *dev; /* Channel device */
- struct resource reg; /* Resource for register */
int irq; /* Channel IRQ */
int id; /* Raw id of this channel */
struct tasklet_struct tasklet;