drv_data->read = drv_data->rx ? chip->read : null_reader;
/* Change speed and bit per word on a per transfer */
----- cr0 = chip->cr0;
----- if (transfer->speed_hz || transfer->bits_per_word) {
-----
----- bits = chip->bits_per_word;
----- speed = chip->speed_hz;
-----
----- if (transfer->speed_hz)
----- speed = transfer->speed_hz;
-----
----- if (transfer->bits_per_word)
----- bits = transfer->bits_per_word;
-----
----- clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed);
-----
----- if (bits <= 8) {
----- drv_data->n_bytes = 1;
----- drv_data->read = drv_data->read != null_reader ?
----- u8_reader : null_reader;
----- drv_data->write = drv_data->write != null_writer ?
----- u8_writer : null_writer;
----- } else if (bits <= 16) {
----- drv_data->n_bytes = 2;
----- drv_data->read = drv_data->read != null_reader ?
----- u16_reader : null_reader;
----- drv_data->write = drv_data->write != null_writer ?
----- u16_writer : null_writer;
----- } else if (bits <= 32) {
----- drv_data->n_bytes = 4;
----- drv_data->read = drv_data->read != null_reader ?
----- u32_reader : null_reader;
----- drv_data->write = drv_data->write != null_writer ?
----- u32_writer : null_writer;
----- }
----- /* if bits/word is changed in dma mode, then must check the
----- * thresholds and burst also */
----- if (chip->enable_dma) {
----- if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
----- message->spi,
----- bits, &dma_burst,
----- &dma_thresh))
----- dev_warn_ratelimited(&message->spi->dev,
----- "pump_transfers: DMA burst size reduced to match bits_per_word\n");
----- }
-----
----- cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
+++++ bits = transfer->bits_per_word;
+++++ speed = transfer->speed_hz;
+++++
+++++ clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
+++++
+++++ if (bits <= 8) {
+++++ drv_data->n_bytes = 1;
+++++ drv_data->read = drv_data->read != null_reader ?
+++++ u8_reader : null_reader;
+++++ drv_data->write = drv_data->write != null_writer ?
+++++ u8_writer : null_writer;
+++++ } else if (bits <= 16) {
+++++ drv_data->n_bytes = 2;
+++++ drv_data->read = drv_data->read != null_reader ?
+++++ u16_reader : null_reader;
+++++ drv_data->write = drv_data->write != null_writer ?
+++++ u16_writer : null_writer;
+++++ } else if (bits <= 32) {
+++++ drv_data->n_bytes = 4;
+++++ drv_data->read = drv_data->read != null_reader ?
+++++ u32_reader : null_reader;
+++++ drv_data->write = drv_data->write != null_writer ?
+++++ u32_writer : null_writer;
++++ }
+++++ /*
+++++ * if bits/word is changed in dma mode, then must check the
+++++ * thresholds and burst also
+++++ */
+++++ if (chip->enable_dma) {
+++++ if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
+++++ message->spi,
+++++ bits, &dma_burst,
+++++ &dma_thresh))
+++++ dev_warn_ratelimited(&message->spi->dev,
+++++ "pump_transfers: DMA burst size reduced to match bits_per_word\n");
+ }
+
+++++ /* NOTE: PXA25x_SSP _could_ use external clocking ... */
+++++ cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
+++++ if (!pxa25x_ssp_comp(drv_data))
+++++ dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
+++++ drv_data->master->max_speed_hz
+++++ / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
+++++ chip->enable_dma ? "DMA" : "PIO");
+++++ else
+++++ dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
+++++ drv_data->master->max_speed_hz / 2
+++++ / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
+++++ chip->enable_dma ? "DMA" : "PIO");
++++
message->state = RUNNING_STATE;
drv_data->dma_mapped = 0;