drm/amd/powerplay: enable voltage control by default for dgpu.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index febee267ff7cac05307671ab8de7d01c1a00cdda..356b7c437022fa54957f2af1f85e8a191648865e 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -80,20 +80,17 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
                switch (hwmgr->chip_id) {
                case CHIP_TOPAZ:
                        topaz_set_asic_special_caps(hwmgr);
-                       hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK |
-                                               PP_VBI_TIME_SUPPORT_MASK |
+                       hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
                                                PP_ENABLE_GFX_CG_THRU_SMU);
                        hwmgr->pp_table_version = PP_TABLE_V0;
                        break;
                case CHIP_TONGA:
                        tonga_set_asic_special_caps(hwmgr);
-                       hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK |
-                                               PP_VBI_TIME_SUPPORT_MASK);
+                       hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
                        break;
                case CHIP_FIJI:
                        fiji_set_asic_special_caps(hwmgr);
-                       hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK |
-                                               PP_VBI_TIME_SUPPORT_MASK |
+                       hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
                                                PP_ENABLE_GFX_CG_THRU_SMU);
                        break;
                case CHIP_POLARIS11: