iwlwifi: HW bug fixes
authorTomas Winkler <tomas.winkler@intel.com>
Mon, 4 Aug 2008 08:00:39 +0000 (16:00 +0800)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 4 Aug 2008 19:09:12 +0000 (15:09 -0400)
This patch adds few HW bug fixes.

Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Zhu Yi <yi.zhu@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/iwlwifi/iwl-5000.c
drivers/net/wireless/iwlwifi/iwl-csr.h
drivers/net/wireless/iwlwifi/iwl-prph.h
net/mac80211/mlme.c

index f7bbd12193f9e6c8ad7ddad89b7d055ce1bad4b6..1d793c093f1a2f9f705438183817ac3fc1c36cca 100644 (file)
@@ -93,6 +93,13 @@ static int iwl5000_apm_init(struct iwl_priv *priv)
        iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
                    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 
+       /* Set FH wait treshold to maximum (HW error during stress W/A) */
+       iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
+
+       /* enable HAP INTA to move device L1a -> L0s */
+       iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
+                   CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
+
        iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 
        /* set "initialization complete" bit to move adapter
@@ -230,6 +237,14 @@ static void iwl5000_nic_config(struct iwl_priv *priv)
                    CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
                    CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 
+       /* W/A : NIC is stuck in a reset state after Early PCIe power off
+        * (PCIe power is lost before PERST# is asserted),
+        * causing ME FW to lose ownership and not being able to obtain it back.
+        */
+        iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
+                               APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
+                               ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
+
        spin_unlock_irqrestore(&priv->lock, flags);
 }
 
index 545ed692d889b36125db3f1c841c1c4d0542188c..52629fbd835a19e199d5a821bb3c31ac1b09020a 100644 (file)
  *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
  */
 #define CSR_HW_REV_WA_REG      (CSR_BASE+0x22C)
+#define CSR_DBG_HPET_MEM_REG   (CSR_BASE+0x240)
 
 /* Bits for CSR_HW_IF_CONFIG_REG */
 #define CSR49_HW_IF_CONFIG_REG_BIT_4965_R      (0x00000010)
 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A    (0x00000000)
 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B    (0x00001000)
 
-#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM     (0x00200000)
+#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A          (0x00080000)
+#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM                (0x00200000)
+#define CSR_HW_IF_CONFIG_REG_BIT_PCI_OWN_SEM           (0x00400000)
+#define CSR_HW_IF_CONFIG_REG_BIT_ME_OWN                        (0x02000000)
+#define CSR_HW_IF_CONFIG_REG_BIT_WAKE_ME               (0x08000000)
+
 
 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
  * acknowledged (reset) by host writing "1" to flagged bits. */
 #define CSR39_ANA_PLL_CFG_VAL        (0x01000000)
 #define CSR50_ANA_PLL_CFG_VAL        (0x00880300)
 
+/* HPET MEM debug */
+#define CSR_DBG_HPET_MEM_REG_VAL       (0xFFFF0000)
 /*=== HBUS (Host-side Bus) ===*/
 #define HBUS_BASE      (0x400)
 /*
index 70d9c7568b981cc38cb505bc9e4bb97c2b6355e3..ee5afd48d3af035ed22527c29c1b98264216077d 100644 (file)
 #define APMG_CLK_VAL_DMA_CLK_RQT       (0x00000200)
 #define APMG_CLK_VAL_BSM_CLK_RQT       (0x00000800)
 
-#define APMG_PS_CTRL_VAL_RESET_REQ     (0x04000000)
 
-#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
+#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS   (0x00400000)
+#define APMG_PS_CTRL_VAL_RESET_REQ             (0x04000000)
+#define APMG_PS_CTRL_MSK_PWR_SRC               (0x03000000)
+#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN         (0x00000000)
+#define APMG_PS_CTRL_VAL_PWR_SRC_MAX           (0x01000000) /* 3945 only */
+#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX          (0x02000000)
 
-#define APMG_PS_CTRL_MSK_PWR_SRC              (0x03000000)
-#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN        (0x00000000)
-#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX         (0x01000000)
 
+#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS         (0x00000800)
 
 /**
  * BSM (Bootstrap State Machine)
index 5358420d8796e5612418d6d5fc2f60d2152d7a3e..e1d11c9b6729e0145866ab9df120ada75601fda1 100644 (file)
@@ -3920,7 +3920,7 @@ done:
        if (sdata->vif.type == IEEE80211_IF_TYPE_IBSS) {
                struct ieee80211_if_sta *ifsta = &sdata->u.sta;
                if (!(ifsta->flags & IEEE80211_STA_BSSID_SET) ||
-                   (!ifsta->state == IEEE80211_IBSS_JOINED &&
+                   (!(ifsta->state == IEEE80211_IBSS_JOINED) &&
                    !ieee80211_sta_active_ibss(dev)))
                        ieee80211_sta_find_ibss(dev, ifsta);
        }