clk: exynos4: Add missing mout_mipihsi clock

This patch adds missing output of mux MIPIHSI which is needed for
div_mipihsi clock.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 8edd64cb18a838abb53a9c100c64dcd2d2464433..42c098df2e22dd147ee542405eb50857c4daf6f9 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -381,6 +381,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
        MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
        MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
        MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
+       MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
        MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
        MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
        MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),