drm/i915: Kill off dead code from skl_dpll0_enable()

We calculate the CDCLK_CTL value from scratch so no need to attempt
some form of RMW first.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1462995892-32416-10-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a6bdabc7cbea43d71122d2b9725358c189889d3d..76934a5a7c49c0bc90b83e65e7844193b29755a7 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5562,17 +5562,12 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
        u32 val;
 
        /* select the minimum CDCLK before enabling DPLL 0 */
-       val = I915_READ(CDCLK_CTL);
-       val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
-       val |= CDCLK_FREQ_337_308;
-
        if (required_vco == 8640)
                min_freq = 308570;
        else
                min_freq = 337500;
 
        val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
-
        I915_WRITE(CDCLK_CTL, val);
        POSTING_READ(CDCLK_CTL);