tile: remove homegrown L1_CACHE_ALIGN macro
authorFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Tue, 29 Jun 2010 07:32:42 +0000 (16:32 +0900)
committerChris Metcalf <cmetcalf@tilera.com>
Tue, 6 Jul 2010 17:41:57 +0000 (13:41 -0400)
Let's use the standard L1_CACHE_ALIGN macro instead.

Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: Chris Metcalf <cmetcalf@tilera.com>
arch/tile/include/asm/cache.h

index c2b7dcfe53271000ce5cd01ee0ea8a4a9e0f159d..ee597147e5cdd018d7bb9996fc6351c99105d23a 100644 (file)
@@ -20,7 +20,6 @@
 /* bytes per L1 data cache line */
 #define L1_CACHE_SHIFT         CHIP_L1D_LOG_LINE_SIZE()
 #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
-#define L1_CACHE_ALIGN(x)      (((x)+(L1_CACHE_BYTES-1)) & -L1_CACHE_BYTES)
 
 /* bytes per L1 instruction cache line */
 #define L1I_CACHE_SHIFT                CHIP_L1I_LOG_LINE_SIZE()