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drm/i915: Pipe palette registers need an offset on VLV
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 24 Jan 2013 13:29:47 +0000 (15:29 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 24 Jan 2013 22:22:24 +0000 (23:22 +0100)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h patch | blob | blame | history

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2982a3baf0e6c99e5a56da4cd5c18312da6c11c7..693baf90db911e0bd1ed098fae24c6306443c244 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1166,8 +1166,8 @@
  * Palette regs
  */
 
-#define _PALETTE_A             0x0a000
-#define _PALETTE_B             0x0a800
+#define _PALETTE_A             (dev_priv->info->display_mmio_offset + 0xa000)
+#define _PALETTE_B             (dev_priv->info->display_mmio_offset + 0xa800)
 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
 
 /* MCH MMIO space */