PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
+
+ /* hpriv->flags bits */
+ AHCI_FLAG_MSI = (1 << 0),
};
struct ahci_cmd_hdr {
struct ahci_host_priv {
unsigned long flags;
- unsigned int have_msi; /* is PCI MSI enabled? */
u32 cap; /* cache of HOST_CAP register */
u32 port_map; /* cache of HOST_PORTS_IMPL reg */
};
return rc;
}
}
-
- hpriv->flags |= HOST_CAP_64;
} else {
rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
if (rc) {
probe_ent->mmio_base = mmio_base;
probe_ent->private_data = hpriv;
- hpriv->have_msi = have_msi;
+ if (have_msi)
+ hpriv->flags |= AHCI_FLAG_MSI;
/* initialize adapter */
rc = ahci_host_init(probe_ent);
scsi_remove_host(ap->host);
}
- have_msi = hpriv->have_msi;
+ have_msi = hpriv->flags & AHCI_FLAG_MSI;
free_irq(host_set->irq, host_set);
for (i = 0; i < host_set->n_ports; i++) {