RDMA/cxgb3: Fixes for zero STag
authorSteve Wise <swise@opengridcomputing.com>
Tue, 15 Jul 2008 06:48:53 +0000 (23:48 -0700)
committerRoland Dreier <rolandd@cisco.com>
Tue, 15 Jul 2008 06:48:53 +0000 (23:48 -0700)
Handling the zero STag in receive work request requires some extra
logic in the driver:

 - Only set the QP_PRIV bit for kernel mode QPs.

- Add a zero STag build function for recv wrs. The uP needs a PBL
  allocated and passed down in the recv WR so it can construct a HW
  PBL for the zero STag S/G entries.  Note: we need to place a few
  restrictions on zero STag usage because of this:

  1) all SGEs in a recv WR must either be zero STag or not.  No mixing.

  2) an individual SGE length cannot exceed 128MB for a zero-stag SGE.
     This should be OK since it's not really practical to allocate
     such a large chunk of pinned contiguous DMA mapped memory.

- Add an optimized non-zero-STag recv wr format for kernel users.
  This is needed to optimize both zero and non-zero STag cracking in
  the recv path for kernel users.

 - Remove the iwch_ prefix from the static build functions.

 - Bump required FW version.

Signed-off-by: Steve Wise <swise@opengridcomputing.com>
drivers/infiniband/hw/cxgb3/cxio_hal.c
drivers/infiniband/hw/cxgb3/cxio_wr.h
drivers/infiniband/hw/cxgb3/iwch_provider.c
drivers/infiniband/hw/cxgb3/iwch_qp.c
drivers/net/cxgb3/version.h

index 340e4181c76108a86d8277d0c0e5c33a951e2e09..f6d5747153a5282f7318aea8dd1ae31a9057bee7 100644 (file)
@@ -278,7 +278,7 @@ int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
        if (!wq->qpid)
                return -ENOMEM;
 
-       wq->rq = kzalloc(depth * sizeof(u64), GFP_KERNEL);
+       wq->rq = kzalloc(depth * sizeof(struct t3_swrq), GFP_KERNEL);
        if (!wq->rq)
                goto err1;
 
@@ -302,6 +302,7 @@ int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
        if (!kernel_domain)
                wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
                                        (wq->qpid << rdev_p->qpshift);
+       wq->rdev = rdev_p;
        PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __func__,
             wq->qpid, wq->doorbell, (unsigned long long) wq->udb);
        return 0;
@@ -1266,13 +1267,16 @@ proc_cqe:
                wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
                PDBG("%s completing sq idx %ld\n", __func__,
                     Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
-               *cookie = (wq->sq +
-                          Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2))->wr_id;
+               *cookie = wq->sq[Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2)].wr_id;
                wq->sq_rptr++;
        } else {
                PDBG("%s completing rq idx %ld\n", __func__,
                     Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
-               *cookie = *(wq->rq + Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
+               *cookie = wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].wr_id;
+               if (wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].pbl_addr)
+                       cxio_hal_pblpool_free(wq->rdev,
+                               wq->rq[Q_PTR2IDX(wq->rq_rptr,
+                               wq->rq_size_log2)].pbl_addr, T3_STAG0_PBL_SIZE);
                wq->rq_rptr++;
        }
 
index de760e9f1cc6d3116499180f94ab08ec8bf6df4c..04618f7bfbb323fc9cdd3ec44046ebb952813457 100644 (file)
@@ -39,6 +39,9 @@
 
 #define T3_MAX_SGE      4
 #define T3_MAX_INLINE  64
+#define T3_STAG0_PBL_SIZE (2 * T3_MAX_SGE << 3)
+#define T3_STAG0_MAX_PBE_LEN (128 * 1024 * 1024)
+#define T3_STAG0_PAGE_SHIFT 15
 
 #define Q_EMPTY(rptr,wptr) ((rptr)==(wptr))
 #define Q_FULL(rptr,wptr,size_log2)  ( (((wptr)-(rptr))>>(size_log2)) && \
@@ -665,6 +668,11 @@ struct t3_swsq {
        int                     signaled;
 };
 
+struct t3_swrq {
+       __u64                   wr_id;
+       __u32                   pbl_addr;
+};
+
 /*
  * A T3 WQ implements both the SQ and RQ.
  */
@@ -681,14 +689,15 @@ struct t3_wq {
        u32 sq_wptr;                    /* sq_wptr - sq_rptr == count of */
        u32 sq_rptr;                    /* pending wrs */
        u32 sq_size_log2;               /* sq size */
-       u64 *rq;                        /* SW RQ (holds consumer wr_ids */
+       struct t3_swrq *rq;             /* SW RQ (holds consumer wr_ids */
        u32 rq_wptr;                    /* rq_wptr - rq_rptr == count of */
        u32 rq_rptr;                    /* pending wrs */
-       u64 *rq_oldest_wr;              /* oldest wr on the SW RQ */
+       struct t3_swrq *rq_oldest_wr;   /* oldest wr on the SW RQ */
        u32 rq_size_log2;               /* rq size */
        u32 rq_addr;                    /* rq adapter address */
        void __iomem *doorbell;         /* kernel db */
        u64 udb;                        /* user db if any */
+       struct cxio_rdev *rdev;
 };
 
 struct t3_cq {
index 7ecfd4d638c584ce27647c2b0ec831efebce6efd..b89640aa6e103e00edd9644ab6a806ff1c30c8c6 100644 (file)
@@ -1007,10 +1007,10 @@ static struct ib_qp *iwch_create_qp(struct ib_pd *pd,
        qhp->ibqp.qp_num = qhp->wq.qpid;
        init_timer(&(qhp->timer));
        PDBG("%s sq_num_entries %d, rq_num_entries %d "
-            "qpid 0x%0x qhp %p dma_addr 0x%llx size %d\n",
+            "qpid 0x%0x qhp %p dma_addr 0x%llx size %d rq_addr 0x%x\n",
             __func__, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
             qhp->wq.qpid, qhp, (unsigned long long) qhp->wq.dma_addr,
-            1 << qhp->wq.size_log2);
+            1 << qhp->wq.size_log2, qhp->wq.rq_addr);
        return &qhp->ibqp;
 }
 
index 3b44300a3036cf46cc28567f428f27f5d9d050c2..9a3be3a9d5dc8f931e7189b7b9f46a9f6b8125fd 100644 (file)
 #include "iwch.h"
 #include "iwch_cm.h"
 #include "cxio_hal.h"
+#include "cxio_resource.h"
 
 #define NO_SUPPORT -1
 
-static int iwch_build_rdma_send(union t3_wr *wqe, struct ib_send_wr *wr,
+static int build_rdma_send(union t3_wr *wqe, struct ib_send_wr *wr,
                                u8 * flit_cnt)
 {
        int i;
@@ -81,7 +82,7 @@ static int iwch_build_rdma_send(union t3_wr *wqe, struct ib_send_wr *wr,
        return 0;
 }
 
-static int iwch_build_rdma_write(union t3_wr *wqe, struct ib_send_wr *wr,
+static int build_rdma_write(union t3_wr *wqe, struct ib_send_wr *wr,
                                 u8 *flit_cnt)
 {
        int i;
@@ -122,7 +123,7 @@ static int iwch_build_rdma_write(union t3_wr *wqe, struct ib_send_wr *wr,
        return 0;
 }
 
-static int iwch_build_rdma_read(union t3_wr *wqe, struct ib_send_wr *wr,
+static int build_rdma_read(union t3_wr *wqe, struct ib_send_wr *wr,
                                u8 *flit_cnt)
 {
        if (wr->num_sge > 1)
@@ -143,7 +144,7 @@ static int iwch_build_rdma_read(union t3_wr *wqe, struct ib_send_wr *wr,
        return 0;
 }
 
-static int iwch_build_fastreg(union t3_wr *wqe, struct ib_send_wr *wr,
+static int build_fastreg(union t3_wr *wqe, struct ib_send_wr *wr,
                                u8 *flit_cnt, int *wr_cnt, struct t3_wq *wq)
 {
        int i;
@@ -185,7 +186,7 @@ static int iwch_build_fastreg(union t3_wr *wqe, struct ib_send_wr *wr,
        return 0;
 }
 
-static int iwch_build_inv_stag(union t3_wr *wqe, struct ib_send_wr *wr,
+static int build_inv_stag(union t3_wr *wqe, struct ib_send_wr *wr,
                                u8 *flit_cnt)
 {
        wqe->local_inv.stag = cpu_to_be32(wr->ex.invalidate_rkey);
@@ -244,23 +245,106 @@ static int iwch_sgl2pbl_map(struct iwch_dev *rhp, struct ib_sge *sg_list,
        return 0;
 }
 
-static int iwch_build_rdma_recv(struct iwch_dev *rhp, union t3_wr *wqe,
+static int build_rdma_recv(struct iwch_qp *qhp, union t3_wr *wqe,
                                struct ib_recv_wr *wr)
 {
-       int i;
-       if (wr->num_sge > T3_MAX_SGE)
-               return -EINVAL;
+       int i, err = 0;
+       u32 pbl_addr[T3_MAX_SGE];
+       u8 page_size[T3_MAX_SGE];
+
+       err = iwch_sgl2pbl_map(qhp->rhp, wr->sg_list, wr->num_sge, pbl_addr,
+                              page_size);
+       if (err)
+               return err;
+       wqe->recv.pagesz[0] = page_size[0];
+       wqe->recv.pagesz[1] = page_size[1];
+       wqe->recv.pagesz[2] = page_size[2];
+       wqe->recv.pagesz[3] = page_size[3];
        wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
        for (i = 0; i < wr->num_sge; i++) {
                wqe->recv.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
                wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
+
+               /* to in the WQE == the offset into the page */
+               wqe->recv.sgl[i].to = cpu_to_be64(((u32) wr->sg_list[i].addr) %
+                               (1UL << (12 + page_size[i])));
+
+               /* pbl_addr is the adapters address in the PBL */
+               wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_addr[i]);
+       }
+       for (; i < T3_MAX_SGE; i++) {
+               wqe->recv.sgl[i].stag = 0;
+               wqe->recv.sgl[i].len = 0;
+               wqe->recv.sgl[i].to = 0;
+               wqe->recv.pbl_addr[i] = 0;
+       }
+       qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
+                            qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
+       qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
+                            qhp->wq.rq_size_log2)].pbl_addr = 0;
+       return 0;
+}
+
+static int build_zero_stag_recv(struct iwch_qp *qhp, union t3_wr *wqe,
+                               struct ib_recv_wr *wr)
+{
+       int i;
+       u32 pbl_addr;
+       u32 pbl_offset;
+
+
+       /*
+        * The T3 HW requires the PBL in the HW recv descriptor to reference
+        * a PBL entry.  So we allocate the max needed PBL memory here and pass
+        * it to the uP in the recv WR.  The uP will build the PBL and setup
+        * the HW recv descriptor.
+        */
+       pbl_addr = cxio_hal_pblpool_alloc(&qhp->rhp->rdev, T3_STAG0_PBL_SIZE);
+       if (!pbl_addr)
+               return -ENOMEM;
+
+       /*
+        * Compute the 8B aligned offset.
+        */
+       pbl_offset = (pbl_addr - qhp->rhp->rdev.rnic_info.pbl_base) >> 3;
+
+       wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
+
+       for (i = 0; i < wr->num_sge; i++) {
+
+               /*
+                * Use a 128MB page size. This and an imposed 128MB
+                * sge length limit allows us to require only a 2-entry HW
+                * PBL for each SGE.  This restriction is acceptable since
+                * since it is not possible to allocate 128MB of contiguous
+                * DMA coherent memory!
+                */
+               if (wr->sg_list[i].length > T3_STAG0_MAX_PBE_LEN)
+                       return -EINVAL;
+               wqe->recv.pagesz[i] = T3_STAG0_PAGE_SHIFT;
+
+               /*
+                * T3 restricts a recv to all zero-stag or all non-zero-stag.
+                */
+               if (wr->sg_list[i].lkey != 0)
+                       return -EINVAL;
+               wqe->recv.sgl[i].stag = 0;
+               wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
                wqe->recv.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
+               wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_offset);
+               pbl_offset += 2;
        }
        for (; i < T3_MAX_SGE; i++) {
+               wqe->recv.pagesz[i] = 0;
                wqe->recv.sgl[i].stag = 0;
                wqe->recv.sgl[i].len = 0;
                wqe->recv.sgl[i].to = 0;
+               wqe->recv.pbl_addr[i] = 0;
        }
+       qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
+                            qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
+       qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
+                            qhp->wq.rq_size_log2)].pbl_addr = pbl_addr;
        return 0;
 }
 
@@ -312,18 +396,18 @@ int iwch_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
                        if (wr->send_flags & IB_SEND_FENCE)
                                t3_wr_flags |= T3_READ_FENCE_FLAG;
                        t3_wr_opcode = T3_WR_SEND;
-                       err = iwch_build_rdma_send(wqe, wr, &t3_wr_flit_cnt);
+                       err = build_rdma_send(wqe, wr, &t3_wr_flit_cnt);
                        break;
                case IB_WR_RDMA_WRITE:
                case IB_WR_RDMA_WRITE_WITH_IMM:
                        t3_wr_opcode = T3_WR_WRITE;
-                       err = iwch_build_rdma_write(wqe, wr, &t3_wr_flit_cnt);
+                       err = build_rdma_write(wqe, wr, &t3_wr_flit_cnt);
                        break;
                case IB_WR_RDMA_READ:
                case IB_WR_RDMA_READ_WITH_INV:
                        t3_wr_opcode = T3_WR_READ;
                        t3_wr_flags = 0; /* T3 reads are always signaled */
-                       err = iwch_build_rdma_read(wqe, wr, &t3_wr_flit_cnt);
+                       err = build_rdma_read(wqe, wr, &t3_wr_flit_cnt);
                        if (err)
                                break;
                        sqp->read_len = wqe->read.local_len;
@@ -332,14 +416,14 @@ int iwch_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
                        break;
                case IB_WR_FAST_REG_MR:
                        t3_wr_opcode = T3_WR_FASTREG;
-                       err = iwch_build_fastreg(wqe, wr, &t3_wr_flit_cnt,
+                       err = build_fastreg(wqe, wr, &t3_wr_flit_cnt,
                                                 &wr_cnt, &qhp->wq);
                        break;
                case IB_WR_LOCAL_INV:
                        if (wr->send_flags & IB_SEND_FENCE)
                                t3_wr_flags |= T3_LOCAL_FENCE_FLAG;
                        t3_wr_opcode = T3_WR_INV_STAG;
-                       err = iwch_build_inv_stag(wqe, wr, &t3_wr_flit_cnt);
+                       err = build_inv_stag(wqe, wr, &t3_wr_flit_cnt);
                        break;
                default:
                        PDBG("%s post of type=%d TBD!\n", __func__,
@@ -398,18 +482,24 @@ int iwch_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
                return -EINVAL;
        }
        while (wr) {
+               if (wr->num_sge > T3_MAX_SGE) {
+                       err = -EINVAL;
+                       *bad_wr = wr;
+                       break;
+               }
                idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
                wqe = (union t3_wr *) (qhp->wq.queue + idx);
                if (num_wrs)
-                       err = iwch_build_rdma_recv(qhp->rhp, wqe, wr);
+                       if (wr->sg_list[0].lkey)
+                               err = build_rdma_recv(qhp, wqe, wr);
+                       else
+                               err = build_zero_stag_recv(qhp, wqe, wr);
                else
                        err = -ENOMEM;
                if (err) {
                        *bad_wr = wr;
                        break;
                }
-               qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr, qhp->wq.rq_size_log2)] =
-                       wr->wr_id;
                build_fw_riwrh((void *) wqe, T3_WR_RCV, T3_COMPLETION_FLAG,
                               Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
                               0, sizeof(struct t3_receive_wr) >> 3, T3_SOPEOP);
@@ -810,7 +900,8 @@ static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp,
        init_attr.qp_dma_size = (1UL << qhp->wq.size_log2);
        init_attr.rqe_count = iwch_rqes_posted(qhp);
        init_attr.flags = qhp->attr.mpa_attr.initiator ? MPA_INITIATOR : 0;
-       init_attr.flags |= capable(CAP_NET_BIND_SERVICE) ? PRIV_QP : 0;
+       if (!qhp->ibqp.uobject)
+               init_attr.flags |= PRIV_QP;
        if (peer2peer) {
                init_attr.rtr_type = RTR_READ;
                if (init_attr.ord == 0 && qhp->attr.mpa_attr.initiator)
index a0177fc55e28a9b241dbfdbd39fa5df1f24c268e..29db711303b9040070aa6c2bc54f7295ed520a24 100644 (file)
@@ -38,7 +38,7 @@
 #define DRV_VERSION "1.0-ko"
 
 /* Firmware version */
-#define FW_VERSION_MAJOR 6
+#define FW_VERSION_MAJOR 7
 #define FW_VERSION_MINOR 0
 #define FW_VERSION_MICRO 0
 #endif                         /* __CHELSIO_VERSION_H */