ath5k: Use generic eeprom read from common ath_bus_opts struct.
authorFelix Fietkau <nbd@openwrt.org>
Thu, 2 Dec 2010 09:27:01 +0000 (10:27 +0100)
committerJohn W. Linville <linville@tuxdriver.com>
Thu, 2 Dec 2010 20:17:50 +0000 (15:17 -0500)
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@neratec.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath5k/ath5k.h
drivers/net/wireless/ath/ath5k/eeprom.c
drivers/net/wireless/ath/ath5k/eeprom.h
drivers/net/wireless/ath/ath5k/pci.c

index ee3c0af3ab3c4602b028c4fe668b4c5440a9c30c..5d9fdc2ccfaa3083bde7ed5be2aa0c3f4c8a482b 100644 (file)
@@ -1342,6 +1342,12 @@ static inline void ath5k_read_cachesize(struct ath_common *common, int *csz)
        common->bus_ops->read_cachesize(common, csz);
 }
 
+static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data)
+{
+       struct ath_common *common = ath5k_hw_common(ah);
+       return common->bus_ops->eeprom_read(common, off, data);
+}
+
 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
 {
        u32 retval = 0, bit, i;
index a648957501e20a6b1af9862f906c12ddbb6e61dc..97eaa9a4415ed9f36b18111878689ae135793c7b 100644 (file)
@@ -65,40 +65,6 @@ static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
 * Parsers *
 \*********/
 
-/*
- * Read from eeprom
- */
-static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
-{
-       u32 status, timeout;
-
-       /*
-        * Initialize EEPROM access
-        */
-       if (ah->ah_version == AR5K_AR5210) {
-               AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
-               (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
-       } else {
-               ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
-               AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
-                               AR5K_EEPROM_CMD_READ);
-       }
-
-       for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
-               status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
-               if (status & AR5K_EEPROM_STAT_RDDONE) {
-                       if (status & AR5K_EEPROM_STAT_RDERR)
-                               return -EIO;
-                       *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
-                                       0xffff);
-                       return 0;
-               }
-               udelay(15);
-       }
-
-       return -ETIMEDOUT;
-}
-
 /*
  * Initialize eeprom & capabilities structs
  */
@@ -1769,12 +1735,12 @@ int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
        u16 data;
        int octet, ret;
 
-       ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
+       ret = ath5k_hw_nvram_read(ah, 0x20, &data);
        if (ret)
                return ret;
 
        for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
-               ret = ath5k_hw_eeprom_read(ah, offset, &data);
+               ret = ath5k_hw_nvram_read(ah, offset, &data);
                if (ret)
                        return ret;
 
index c4a6d5f26af4f08ac9b379a22045aaed1a6c5c84..0017006be8414d5f07a83a7f08746efe969ef508 100644 (file)
@@ -241,7 +241,7 @@ enum ath5k_eeprom_freq_bands{
 #define        AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz      6250
 
 #define AR5K_EEPROM_READ(_o, _v) do {                  \
-       ret = ath5k_hw_eeprom_read(ah, (_o), &(_v));    \
+       ret = ath5k_hw_nvram_read(ah, (_o), &(_v));     \
        if (ret)                                        \
                return ret;                             \
 } while (0)
index 9f7d3ca6ea210ae1a9bc332d614d8ea3a761c0b4..3f26cf2001962b0a5bb5539e850ba4ab936b96e7 100644 (file)
@@ -65,10 +65,46 @@ static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
                *csz = L1_CACHE_BYTES >> 2;   /* Use the default size */
 }
 
+/*
+ * Read from eeprom
+ */
+bool ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
+{
+       struct ath5k_hw *ah = (struct ath5k_hw *) common->ah;
+       u32 status, timeout;
+
+       /*
+        * Initialize EEPROM access
+        */
+       if (ah->ah_version == AR5K_AR5210) {
+               AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
+               (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
+       } else {
+               ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
+               AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
+                               AR5K_EEPROM_CMD_READ);
+       }
+
+       for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
+               status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
+               if (status & AR5K_EEPROM_STAT_RDDONE) {
+                       if (status & AR5K_EEPROM_STAT_RDERR)
+                               return -EIO;
+                       *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
+                                       0xffff);
+                       return 0;
+               }
+               udelay(15);
+       }
+
+       return -ETIMEDOUT;
+}
+
 /* Common ath_bus_opts structure */
 static const struct ath_bus_ops ath_pci_bus_ops = {
        .ath_bus_type = ATH_PCI,
        .read_cachesize = ath5k_pci_read_cachesize,
+       .eeprom_read = ath5k_pci_eeprom_read,
 };
 
 /********************\