MIPS: sc-mips: L2 cache is inclusive of L1 dcache for CM3

In systems with CM3 & higher, the L2 cache is inclusive of the L1
dcache. Indicate this such that cpu_has_inclusive_pcaches evaluates true
and we avoid some unnecessary cache ops during DMA cache maintenance.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14018/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 286a4d5a18843c82be783dfde6b12798d191869e..c909c334272945c1c52d812462e78a74c2f1824b 100644 (file)
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -181,6 +181,7 @@ static int __init mips_sc_probe_cm3(void)
 
        if (c->scache.linesz) {
                c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
+               c->options |= MIPS_CPU_INCLUSIVE_CACHES;
                return 1;
        }