projects
/
GitHub
/
LineageOS
/
G12
/
android_kernel_amlogic_linux-4.9.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
bc2ad8f
)
ARM: ux500: add SCU and WD to device tree
author
Linus Walleij
<linus.walleij@linaro.org>
Thu, 14 May 2015 09:22:34 +0000
(11:22 +0200)
committer
Arnd Bergmann
<arnd@arndb.de>
Fri, 15 May 2015 15:22:39 +0000
(17:22 +0200)
The Ux500 like other Cortex-A9 SoC's has a Snoop Control
Unit (SCU) and a Watchdog in the same address range as
the local timers. Add these to the SoC device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arch/arm/boot/dts/ste-dbx5x0.dtsi
patch
|
blob
|
blame
|
history
diff --git
a/arch/arm/boot/dts/ste-dbx5x0.dtsi
b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index 5b876f263af492e1c9e031ba0a6fc23cfaebdc21..f024a1c0de8b57b42de5ec96cad452f39aae23e2 100644
(file)
--- a/
arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/
arch/arm/boot/dts/ste-dbx5x0.dtsi
@@
-185,6
+185,11
@@
<0xa0410100 0x100>;
};
+ scu@a04100000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xa0410000 0x100>;
+ };
+
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0xa0412000 0x1000>;
@@
-245,6
+250,13
@@
clocks = <&smp_twd_clk>;
};
+ watchdog@a0410620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0xa0410620 0x20>;
+ interrupts = <1 14 0x304>;
+ clocks = <&smp_twd_clk>;
+ };
+
rtc@80154000 {
compatible = "arm,rtc-pl031", "arm,primecell";
reg = <0x80154000 0x1000>;