return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
}
+#define PRCMU_A9_MASK_REQ 0x00000328
+#define PRCMU_A9_MASK_REQ_MASK 0x00000001
+#define PRCMU_GIC_DELAY 1
+
+/* This function decouple the gic from the prcmu */
+int db8500_prcmu_gic_decouple(void)
+{
+ u32 val = readl(_PRCMU_BASE + PRCMU_A9_MASK_REQ);
+
+ /* Set bit 0 register value to 1 */
+ writel(val | PRCMU_A9_MASK_REQ_MASK, _PRCMU_BASE + PRCMU_A9_MASK_REQ);
+
+ /* Make sure the register is updated */
+ readl(_PRCMU_BASE + PRCMU_A9_MASK_REQ);
+
+ /* Wait a few cycles for the gic mask completion */
+ udelay(PRCMU_GIC_DELAY);
+
+ return 0;
+}
+
+/* This function recouple the gic with the prcmu */
+int db8500_prcmu_gic_recouple(void)
+{
+ u32 val = readl(_PRCMU_BASE + PRCMU_A9_MASK_REQ);
+
+ /* Set bit 0 register value to 0 */
+ writel(val & ~PRCMU_A9_MASK_REQ_MASK, _PRCMU_BASE + PRCMU_A9_MASK_REQ);
+
+ return 0;
+}
+
/* This function should only be called while mb0_transfer.lock is held. */
static void config_wakeups(void)
{
void db8500_prcmu_system_reset(u16 reset_code);
int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
u8 db8500_prcmu_get_power_state_result(void);
+int db8500_prcmu_gic_decouple(void);
+int db8500_prcmu_gic_recouple(void);
void db8500_prcmu_enable_wakeups(u32 wakeups);
int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
int db8500_prcmu_request_clock(u8 clock, bool enable);
return db8500_prcmu_get_power_state_result();
}
+static inline int prcmu_gic_decouple(void)
+{
+ if (cpu_is_u5500())
+ return -EINVAL;
+ else
+ return db8500_prcmu_gic_decouple();
+}
+
+static inline int prcmu_gic_recouple(void)
+{
+ if (cpu_is_u5500())
+ return -EINVAL;
+ else
+ return db8500_prcmu_gic_recouple();
+}
+
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
if (cpu_is_u5500())