perf, x86: Fix PEBS enable/disable vs cpuc->enabled

We should never call ->enable with the pmu enabled, and we _can_ have
->disable called with the pmu enabled.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 66c6962f15f9783cc95d017d69ed439e19d4de4c..9ad0e67b9c820dd426514e9bda2aef5d2d22edbc 100644 (file)
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -338,7 +338,7 @@ static void intel_pmu_pebs_enable(struct perf_event *event)
        hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 
        val |= 1ULL << hwc->idx;
-       wrmsrl(MSR_IA32_PEBS_ENABLE, val);
+       WARN_ON_ONCE(cpuc->enabled);
 
        if (x86_pmu.intel_cap.pebs_trap)
                intel_pmu_lbr_enable(event);
@@ -351,7 +351,8 @@ static void intel_pmu_pebs_disable(struct perf_event *event)
        u64 val = cpuc->pebs_enabled;
 
        val &= ~(1ULL << hwc->idx);
-       wrmsrl(MSR_IA32_PEBS_ENABLE, val);
+       if (cpuc->enabled)
+               wrmsrl(MSR_IA32_PEBS_ENABLE, val);
 
        hwc->config |= ARCH_PERFMON_EVENTSEL_INT;