};
static const struct mio_regmap m_series_stc_write_regmap[] = {
- [Interrupt_A_Ack_Register] = { 0x104, 2 },
+ [NISTC_INTA_ACK_REG] = { 0x104, 2 },
[Interrupt_B_Ack_Register] = { 0x106, 2 },
[AI_Command_2_Register] = { 0x108, 2 },
[AO_Command_2_Register] = { 0x10a, 2 },
unsigned short ack = 0;
if (a_status & AI_SC_TC_St)
- ack |= AI_SC_TC_Interrupt_Ack;
+ ack |= NISTC_INTA_ACK_AI_SC_TC;
if (a_status & AI_START1_St)
- ack |= AI_START1_Interrupt_Ack;
+ ack |= NISTC_INTA_ACK_AI_START1;
if (a_status & AI_START_St)
- ack |= AI_START_Interrupt_Ack;
+ ack |= NISTC_INTA_ACK_AI_START;
if (a_status & AI_STOP_St)
- /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
- ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */;
+ ack |= NISTC_INTA_ACK_AI_STOP;
if (ack)
- ni_stc_writew(dev, ack, Interrupt_A_Ack_Register);
+ ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
}
static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
* AI_Personal_Register
* AI_Output_Control_Register
*/
- ni_stc_writew(dev,
- AI_SC_TC_Error_Confirm |
- AI_START_Interrupt_Ack |
- AI_START2_Interrupt_Ack |
- AI_START1_Interrupt_Ack |
- AI_SC_TC_Interrupt_Ack |
- AI_Error_Interrupt_Ack |
- AI_STOP_Interrupt_Ack,
- Interrupt_A_Ack_Register); /* clear interrupts */
+
+ /* clear interrupts */
+ ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
}
/* clear interrupts */
- ni_stc_writew(dev,
- AI_Error_Interrupt_Ack |
- AI_STOP_Interrupt_Ack |
- AI_START_Interrupt_Ack |
- AI_START2_Interrupt_Ack |
- AI_START1_Interrupt_Ack |
- AI_SC_TC_Interrupt_Ack |
- AI_SC_TC_Error_Confirm,
- Interrupt_A_Ack_Register);
+ ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
ni_set_bits(dev, Interrupt_A_Enable_Register,
interrupt_a_enable, 1);
[NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
[NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
[NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
- [NITIO_G0_INT_ACK] = { Interrupt_A_Ack_Register, 2 },
+ [NITIO_G0_INT_ACK] = { NISTC_INTA_ACK_REG, 2 },
[NITIO_G1_INT_ACK] = { Interrupt_B_Ack_Register, 2 },
[NITIO_G0_STATUS] = { AI_Status_1_Register, 2 },
[NITIO_G1_STATUS] = { AO_Status_1_Register, 2 },
#define NUM_PFI_OUTPUT_SELECT_REGS 6
-/* Registers in the National Instruments DAQ-STC chip */
-
-#define Interrupt_A_Ack_Register 2
-#define G0_Gate_Interrupt_Ack _bit15
-#define G0_TC_Interrupt_Ack _bit14
-#define AI_Error_Interrupt_Ack _bit13
-#define AI_STOP_Interrupt_Ack _bit12
-#define AI_START_Interrupt_Ack _bit11
-#define AI_START2_Interrupt_Ack _bit10
-#define AI_START1_Interrupt_Ack _bit9
-#define AI_SC_TC_Interrupt_Ack _bit8
-#define AI_SC_TC_Error_Confirm _bit7
-#define G0_TC_Error_Confirm _bit6
-#define G0_Gate_Error_Confirm _bit5
+/*
+ * Registers in the National Instruments DAQ-STC chip
+ */
+
+#define NISTC_INTA_ACK_REG 2
+#define NISTC_INTA_ACK_G0_GATE BIT(15)
+#define NISTC_INTA_ACK_G0_TC BIT(14)
+#define NISTC_INTA_ACK_AI_ERR BIT(13)
+#define NISTC_INTA_ACK_AI_STOP BIT(12)
+#define NISTC_INTA_ACK_AI_START BIT(11)
+#define NISTC_INTA_ACK_AI_START2 BIT(10)
+#define NISTC_INTA_ACK_AI_START1 BIT(9)
+#define NISTC_INTA_ACK_AI_SC_TC BIT(8)
+#define NISTC_INTA_ACK_AI_SC_TC_ERR BIT(7)
+#define NISTC_INTA_ACK_G0_TC_ERR BIT(6)
+#define NISTC_INTA_ACK_G0_GATE_ERR BIT(5)
+#define NISTC_INTA_ACK_AI_ALL (NISTC_INTA_ACK_AI_ERR | \
+ NISTC_INTA_ACK_AI_STOP | \
+ NISTC_INTA_ACK_AI_START | \
+ NISTC_INTA_ACK_AI_START2 | \
+ NISTC_INTA_ACK_AI_START1 | \
+ NISTC_INTA_ACK_AI_SC_TC | \
+ NISTC_INTA_ACK_AI_SC_TC_ERR)
#define AI_Status_1_Register 2
#define Interrupt_A_St 0x8000