ARM: dts: socfpga: Enable QSPI on the Arria5 devkit

Enable the QSPI node and add the flash chip.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 3c8867862b0dbece25f0dd5a68ac5bc0f6c2dde1..f739ead074a2b455255d45f38c4bafe82224c415 100644 (file)
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -82,6 +82,39 @@
        status = "okay";
 };
 
+&qspi {
+       status = "okay";
+
+       flash: flash@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "n25q256a";
+               reg = <0>;
+               spi-max-frequency = <100000000>;
+
+               m25p,fast-read;
+               cdns,page-size = <256>;
+               cdns,block-size = <16>;
+               cdns,read-delay = <4>;
+               cdns,tshsl-ns = <50>;
+               cdns,tsd2d-ns = <50>;
+               cdns,tchsh-ns = <4>;
+               cdns,tslch-ns = <4>;
+
+               partition@qspi-boot {
+                       /* 8MB for raw data. */
+                       label = "Flash 0 Raw Data";
+                       reg = <0x0 0x800000>;
+               };
+
+               partition@qspi-rootfs {
+                       /* 120MB for jffs2 data. */
+                       label = "Flash 0 jffs2 Filesystem";
+                       reg = <0x800000 0x7800000>;
+               };
+       };
+};
+
 &usb1 {
        status = "okay";
 };