ath9k_hw: Find the maximum number of chains that hw supports

Have it in ah->caps. This will be used during various
calibrations.

Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 49da1849c7feb510ff15d56bd616dba2b615e3fa..a2f85b75b7f843cb32870a69176b924b6882e790 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1764,7 +1764,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
        struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
 
        u16 capField = 0, eeval;
-       u8 ant_div_ctl1;
+       u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
 
        eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
        regulatory->current_rd = eeval;
@@ -1976,6 +1976,18 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                pCap->pcie_lcr_offset = 0x80;
        }
 
+       tx_chainmask = pCap->tx_chainmask;
+       rx_chainmask = pCap->rx_chainmask;
+       while (tx_chainmask || rx_chainmask) {
+               if (tx_chainmask & BIT(0))
+                       pCap->max_txchains++;
+               if (rx_chainmask & BIT(0))
+                       pCap->max_rxchains++;
+
+               tx_chainmask >>= 1;
+               rx_chainmask >>= 1;
+       }
+
        return 0;
 }
 

diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 76ae3296e3fcfe6d96c16e628fc900b0fdf61b4f..fcfd63efe55a634cc5ca2dc6084f5d933e40720d 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -199,6 +199,8 @@ struct ath9k_hw_capabilities {
        u16 rts_aggr_limit;
        u8 tx_chainmask;
        u8 rx_chainmask;
+       u8 max_txchains;
+       u8 max_rxchains;
        u16 tx_triglevel_max;
        u16 reg_cap;
        u8 num_gpio_pins;