net: mvpp2: Fix clock resource by adding an optional bus clock

On Armada 7K/8K we need to explicitly enable the bus clock. The bus clock
is optional because not all the SoCs need them but at least for Armada
7K/8K it is actually mandatory.

The binding documentation is updating accordingly.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt b/Documentation/devicetree/bindings/net/marvell-pp2.txt
index 7e2dad08a12e92c1baa0290116cbd032f5bb1e88..1814fa13f6ab8078a52a32fa2a55156124d696bb 100644 (file)
--- a/Documentation/devicetree/bindings/net/marvell-pp2.txt
+++ b/Documentation/devicetree/bindings/net/marvell-pp2.txt
@@ -21,8 +21,9 @@ Required properties:
        - main controller clock (for both armada-375-pp2 and armada-7k-pp2)
        - GOP clock (for both armada-375-pp2 and armada-7k-pp2)
        - MG clock (only for armada-7k-pp2)
-- clock-names: names of used clocks, must be "pp_clk", "gop_clk" and
-  "mg_clk" (the latter only for armada-7k-pp2).
+       - AXI clock (only for armada-7k-pp2)
+- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk"
+  and "axi_clk" (the 2 latter only for armada-7k-pp2).
 
 The ethernet ports are represented by subnodes. At least one port is
 required.
@@ -78,8 +79,9 @@ Example for marvell,armada-7k-pp2:
 cpm_ethernet: ethernet@0 {
        compatible = "marvell,armada-7k-pp22";
        reg = <0x0 0x100000>, <0x129000 0xb000>;
-       clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
-       clock-names = "pp_clk", "gop_clk", "gp_clk";
+       clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
+                <&cpm_syscon0 1 5>, <&cpm_syscon0 1 18>;
+       clock-names = "pp_clk", "gop_clk", "gp_clk", "axi_clk";
 
        eth0: eth0 {
                interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,

diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index 1610555647201d13bdda2087ad3f19f85c2513d1..9c86cb7cb988a7ee3f89e3d2ec86a37f0a0344dc 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -793,6 +793,7 @@ struct mvpp2 {
        struct clk *pp_clk;
        struct clk *gop_clk;
        struct clk *mg_clk;
+       struct clk *axi_clk;
 
        /* List of pointers to port structures */
        struct mvpp2_port **port_list;
@@ -7970,6 +7971,18 @@ static int mvpp2_probe(struct platform_device *pdev)
                err = clk_prepare_enable(priv->mg_clk);
                if (err < 0)
                        goto err_gop_clk;
+
+               priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
+               if (IS_ERR(priv->axi_clk)) {
+                       err = PTR_ERR(priv->axi_clk);
+                       if (err == -EPROBE_DEFER)
+                               goto err_gop_clk;
+                       priv->axi_clk = NULL;
+               } else {
+                       err = clk_prepare_enable(priv->axi_clk);
+                       if (err < 0)
+                               goto err_gop_clk;
+               }
        }
 
        /* Get system's tclk rate */
@@ -8024,6 +8037,7 @@ static int mvpp2_probe(struct platform_device *pdev)
        return 0;
 
 err_mg_clk:
+       clk_disable_unprepare(priv->axi_clk);
        if (priv->hw_version == MVPP22)
                clk_disable_unprepare(priv->mg_clk);
 err_gop_clk:
@@ -8061,6 +8075,7 @@ static int mvpp2_remove(struct platform_device *pdev)
                                  aggr_txq->descs_dma);
        }
 
+       clk_disable_unprepare(priv->axi_clk);
        clk_disable_unprepare(priv->mg_clk);
        clk_disable_unprepare(priv->pp_clk);
        clk_disable_unprepare(priv->gop_clk);