static void ppgtt_bind_vma(struct i915_vma *vma,
enum i915_cache_level cache_level,
- u32 flags);
-static void ppgtt_unbind_vma(struct i915_vma *vma);
+ u32 unused)
+{
+ u32 pte_flags = 0;
+
+ /* Currently applicable only to VLV */
+ if (vma->obj->gt_ro)
+ pte_flags |= PTE_READ_ONLY;
+
+ vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
+ cache_level, pte_flags);
+}
+
+static void ppgtt_unbind_vma(struct i915_vma *vma)
+{
+ vma->vm->clear_range(vma->vm,
+ vma->node.start,
+ vma->obj->base.size,
+ true);
+}
static inline gen8_pte_t gen8_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
kfree(ppgtt);
}
-static void
-ppgtt_bind_vma(struct i915_vma *vma,
- enum i915_cache_level cache_level,
- u32 unused)
-{
- u32 pte_flags = 0;
-
- /* Currently applicable only to VLV */
- if (vma->obj->gt_ro)
- pte_flags |= PTE_READ_ONLY;
-
- vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
- cache_level, pte_flags);
-}
-
-static void ppgtt_unbind_vma(struct i915_vma *vma)
-{
- vma->vm->clear_range(vma->vm,
- vma->node.start,
- vma->obj->base.size,
- true);
-}
-
extern int intel_iommu_gfx_mapped;
/* Certain Gen5 chipsets require require idling the GPU before
* unmapping anything from the GTT when VT-d is enabled.