[9610] arm64: dtsi: add coresight entry

Change-Id: Ie6761967ce0f0a48b3b27ca0eaff03bd5de7a598
Signed-off-by: Donghyeok Choe <d7271.choe@samsung.com>

diff --git a/arch/arm64/boot/dts/exynos/exynos9610-debug.dtsi b/arch/arm64/boot/dts/exynos/exynos9610-debug.dtsi
index 5fc1c3bd17f3331466635c99e0863297a227b130..6a7813581e1248e5e74e233eab08fc6494f86f22 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos9610-debug.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos9610-debug.dtsi
@@ -41,4 +41,42 @@
        exynos-helper {
                compatible = "samsung,exynos-helper";
        };
+
+        coresight@16000000 {
+               compatible = "exynos,coresight";
+               base = <0x16000000>;
+               sj-offset = <0x6000>;
+               cl0_cpu0@400000 {
+                       device_type = "cs";
+                       dbg-offset = <0x410000>;
+               };
+               cl0_cpu1@500000 {
+                       device_type = "cs";
+                       dbg-offset = <0x510000>;
+               };
+               cl0_cpu2@600000 {
+                       device_type = "cs";
+                       dbg-offset = <0x610000>;
+               };
+               cl0_cpu3@700000 {
+                       device_type = "cs";
+                       dbg-offset = <0x710000>;
+               };
+               cl1_cpu0@800000 {
+                       device_type = "cs";
+                       dbg-offset = <0x810000>;
+               };
+               cl1_cpu1@900000 {
+                       device_type = "cs";
+                       dbg-offset = <0x910000>;
+               };
+               cl1_cpu2@a00000 {
+                       device_type = "cs";
+                       dbg-offset = <0xa10000>;
+               };
+               cl1_cpu3@b00000 {
+                       device_type = "cs";
+                       dbg-offset = <0xb10000>;
+               };
+       };
 };