drm/i915: Clamp efficient frequency to valid range

The efficient frequency (RPe) should stay in the range
RPn <= RPe <= RP0.  The pcode clamps the returned value
internally on Broadwell but not on Haswell.

Fix for missing range check in
commit 93ee29203f506582cca2bcec5f05041526d9ab0a
Author: Tom O'Rourke <Tom.O'Rourke@intel.com>
Date:   Wed Nov 19 14:21:52 2014 -0800

    drm/i915: Use efficient frequency for HSW/BDW

Reference: http://lists.freedesktop.org/archives/intel-gfx/2015-February/059802.html
Reported-by: Michael Auchter <a@phire.org>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@vger.kernel.org # v3.19
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6ece663f3394bca7ed2bc7b317520ad54b2c1a56..24d77ddcc5f47bc648309068cb81f69464aeb305 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4005,7 +4005,10 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
                                        &ddcc_status);
                if (0 == ret)
                        dev_priv->rps.efficient_freq =
-                               (ddcc_status >> 8) & 0xff;
+                               clamp_t(u8,
+                                       ((ddcc_status >> 8) & 0xff),
+                                       dev_priv->rps.min_freq,
+                                       dev_priv->rps.max_freq);
        }
 
        /* Preserve min/max settings in case of re-init */