ARM: OMAP4+: Remove un-necessary cacheflush in secondary CPU boot path

This was borrowed from ARM versatile code with pen_release mechanism but since
OMAP uses hardware register based synchronisation, pen_release stuff was
dropped. Unfortunately the cacheflush wasn't dropped along with it.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index d9727218dd0a3089792a1ef25737987ce9034f5b..5d8f2497017edb1755c75424c661fb912c453c3b 100644 (file)
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -21,7 +21,6 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 
-#include <asm/cacheflush.h>
 #include <asm/smp_scu.h>
 
 #include "omap-secure.h"
@@ -103,9 +102,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
        else
                __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
 
-       flush_cache_all();
-       smp_wmb();
-
        if (!cpu1_clkdm)
                cpu1_clkdm = clkdm_lookup("mpu1_clkdm");