MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
#endif
-/*
+/* s3c24xx_get_device_quirks
+ *
* Get controller type either from device tree or platform device variant.
- */
+*/
+
static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
{
if (pdev->dev.of_node) {
const struct of_device_id *match;
-
match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
return (kernel_ulong_t)match->data;
}
return platform_get_device_id(pdev)->driver_data;
}
-/*
- * Complete the message and wake up the caller, using the given return code,
+/* s3c24xx_i2c_master_complete
+ *
+ * complete the message and wake up the caller, using the given return code,
* or zero to mean ok.
- */
+*/
+
static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
{
dev_dbg(i2c->dev, "master_complete %d\n", ret);
}
/* irq enable/disable functions */
+
static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
{
unsigned long tmp;
return false;
}
-/*
+/* s3c24xx_i2c_message_start
+ *
* put the start of a message onto the bus
- */
+*/
+
static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
struct i2c_msg *msg)
{
dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
writeb(addr, i2c->regs + S3C2410_IICDS);
- /*
- * delay here to ensure the data byte has gotten onto the bus
- * before the transaction is started
- */
+ /* delay here to ensure the data byte has gotten onto the bus
+ * before the transaction is started */
+
ndelay(i2c->tx_setup);
dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
s3c24xx_i2c_disable_irq(i2c);
}
-/*
- * helper functions to determine the current state in the set of
- * messages we are sending
- */
+/* helper functions to determine the current state in the set of
+ * messages we are sending */
-/*
+/* is_lastmsg()
+ *
* returns TRUE if the current message is the last in the set
- */
+*/
+
static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
{
return i2c->msg_idx >= (i2c->msg_num - 1);
}
-/*
+/* is_msglast
+ *
* returns TRUE if we this is the last byte in the current message
- */
+*/
+
static inline int is_msglast(struct s3c24xx_i2c *i2c)
{
- /*
- * msg->len is always 1 for the first byte of smbus block read.
+ /* msg->len is always 1 for the first byte of smbus block read.
* Actual length will be read from slave. More bytes will be
- * read according to the length then.
- */
+ * read according to the length then. */
if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
return 0;
return i2c->msg_ptr == i2c->msg->len-1;
}
-/*
+/* is_msgend
+ *
* returns TRUE if we reached the end of the current message
- */
+*/
+
static inline int is_msgend(struct s3c24xx_i2c *i2c)
{
return i2c->msg_ptr >= i2c->msg->len;
}
-/*
+/* i2c_s3c_irq_nextbyte
+ *
* process an interrupt and work out what to do
*/
+
static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
{
unsigned long tmp;
goto out_ack;
case STATE_START:
- /*
- * last thing we did was send a start condition on the
+ /* last thing we did was send a start condition on the
* bus, or started a new i2c message
*/
+
if (iicstat & S3C2410_IICSTAT_LASTBIT &&
!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
/* ack was not received... */
+
dev_dbg(i2c->dev, "ack was not received\n");
s3c24xx_i2c_stop(i2c, -ENXIO);
goto out_ack;
else
i2c->state = STATE_WRITE;
- /*
- * Terminate the transfer if there is nothing to do
- * as this is used by the i2c probe to find devices.
- */
+ /* terminate the transfer if there is nothing to do
+ * as this is used by the i2c probe to find devices. */
+
if (is_lastmsg(i2c) && i2c->msg->len == 0) {
s3c24xx_i2c_stop(i2c, 0);
goto out_ack;
if (i2c->state == STATE_READ)
goto prepare_read;
- /*
- * fall through to the write state, as we will need to
- * send a byte as well
- */
+ /* fall through to the write state, as we will need to
+ * send a byte as well */
case STATE_WRITE:
- /*
- * we are writing data to the device... check for the
+ /* we are writing data to the device... check for the
* end of the message, and if so, work out what to do
*/
+
if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
if (iicstat & S3C2410_IICSTAT_LASTBIT) {
dev_dbg(i2c->dev, "WRITE: No Ack\n");
byte = i2c->msg->buf[i2c->msg_ptr++];
writeb(byte, i2c->regs + S3C2410_IICDS);
- /*
- * delay after writing the byte to allow the
+ /* delay after writing the byte to allow the
* data setup time on the bus, as writing the
* data to the register causes the first bit
* to appear on SDA, and SCL will change as
- * soon as the interrupt is acknowledged
- */
+ * soon as the interrupt is acknowledged */
+
ndelay(i2c->tx_setup);
} else if (!is_lastmsg(i2c)) {
if (i2c->msg->flags & I2C_M_NOSTART) {
if (i2c->msg->flags & I2C_M_RD) {
- /*
- * cannot do this, the controller
+ /* cannot do this, the controller
* forces us to send a new START
- * when we change direction
- */
+ * when we change direction */
+
s3c24xx_i2c_stop(i2c, -EINVAL);
}
} else {
/* send stop */
+
s3c24xx_i2c_stop(i2c, 0);
}
break;
case STATE_READ:
- /*
- * we have a byte of data in the data register, do
+ /* we have a byte of data in the data register, do
* something with it, and then work out whether we are
* going to do any more read/write
*/
+
byte = readb(i2c->regs + S3C2410_IICDS);
i2c->msg->buf[i2c->msg_ptr++] = byte;
s3c24xx_i2c_disable_ack(i2c);
} else if (is_msgend(i2c)) {
- /*
- * ok, we've read the entire buffer, see if there
- * is anything else we need to do
- */
+ /* ok, we've read the entire buffer, see if there
+ * is anything else we need to do */
+
if (is_lastmsg(i2c)) {
/* last message, send stop and complete */
dev_dbg(i2c->dev, "READ: Send Stop\n");
return ret;
}
-/*
+/* s3c24xx_i2c_irq
+ *
* top level IRQ servicing routine
- */
+*/
+
static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
{
struct s3c24xx_i2c *i2c = dev_id;
goto out;
}
- /*
- * pretty much this leaves us with the fact that we've
- * transmitted or received whatever byte we last sent
- */
+ /* pretty much this leaves us with the fact that we've
+ * transmitted or received whatever byte we last sent */
+
i2c_s3c_irq_nextbyte(i2c, status);
out:
}
-/*
+/* s3c24xx_i2c_set_master
+ *
* get the i2c bus for a master transaction
- */
+*/
+
static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
{
unsigned long iicstat;
return -ETIMEDOUT;
}
-/*
+/* s3c24xx_i2c_wait_idle
+ *
* wait for the i2c bus to become idle.
- */
+*/
+
static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
{
unsigned long iicstat;
dev_warn(i2c->dev, "timeout waiting for bus idle\n");
}
-/*
+/* s3c24xx_i2c_doxfer
+ *
* this starts an i2c transfer
- */
+*/
+
static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
struct i2c_msg *msgs, int num)
{
ret = i2c->msg_idx;
- /*
- * Having these next two as dev_err() makes life very
- * noisy when doing an i2cdetect
- */
+ /* having these next two as dev_err() makes life very
+ * noisy when doing an i2cdetect */
+
if (timeout == 0)
dev_dbg(i2c->dev, "timeout\n");
else if (ret != num)
return ret;
}
-/*
+/* s3c24xx_i2c_xfer
+ *
* first port of call from the i2c bus code when an message needs
* transferring across the i2c bus.
- */
+*/
+
static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
struct i2c_msg *msgs, int num)
{
int retry;
int ret;
+ pm_runtime_get_sync(&adap->dev);
ret = clk_enable(i2c->clk);
if (ret)
return ret;
if (ret != -EAGAIN) {
clk_disable(i2c->clk);
+ pm_runtime_put(&adap->dev);
return ret;
}
}
clk_disable(i2c->clk);
+ pm_runtime_put(&adap->dev);
return -EREMOTEIO;
}
}
/* i2c bus registration info */
+
static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
.master_xfer = s3c24xx_i2c_xfer,
.functionality = s3c24xx_i2c_func,
};
-/*
+/* s3c24xx_i2c_calcdivisor
+ *
* return the divisor settings for a given frequency
- */
+*/
+
static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
unsigned int *div1, unsigned int *divs)
{
return clkin / (calc_divs * calc_div1);
}
-/*
+/* s3c24xx_i2c_clockrate
+ *
* work out a divisor for the user requested frequency setting,
* either by the requested frequency, or scanning the acceptable
* range of frequencies until something is found
- */
+*/
+
static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
{
struct s3c2410_platform_i2c *pdata = i2c->pdata;
i2c_unlock_adapter(&i2c->adap);
if (ret < 0)
- dev_err(i2c->dev, "cannot find frequency (%d)\n", ret);
+ dev_err(i2c->dev, "cannot find frequency\n");
else
dev_info(i2c->dev, "setting freq %d\n", got);
}
ret = gpio_request(gpio, "i2c-bus");
if (ret) {
- dev_err(i2c->dev, "gpio [%d] request failed (%d)\n",
- gpio, ret);
+ dev_err(i2c->dev, "gpio [%d] request failed\n", gpio);
goto free_gpio;
}
}
}
#endif
-/*
+/* s3c24xx_i2c_init
+ *
* initialise the controller, set the IO lines and frequency
- */
+*/
+
static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
{
struct s3c2410_platform_i2c *pdata;
}
#ifdef CONFIG_OF
-/*
+/* s3c24xx_i2c_parse_dt
+ *
* Parse the device tree node and retreive the platform data.
- */
+*/
+
static void
s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
{
}
#else
static void
-s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
+s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
+{
+ return;
+}
#endif
+/* s3c24xx_i2c_probe
+ *
+ * called by the bus driver when a suitable device is found
+*/
+
static int s3c24xx_i2c_probe(struct platform_device *pdev)
{
struct s3c24xx_i2c *i2c;
init_waitqueue_head(&i2c->wait);
/* find the clock and enable it */
+
i2c->dev = &pdev->dev;
i2c->clk = devm_clk_get(&pdev->dev, "i2c");
if (IS_ERR(i2c->clk)) {
dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
+
/* map the registers */
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
i2c->regs = devm_ioremap_resource(&pdev->dev, res);
i2c->regs, res);
/* setup info block for the i2c core */
+
i2c->adap.algo_data = i2c;
i2c->adap.dev.parent = &pdev->dev;
+
i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
/* inititalise the i2c gpio lines */
- if (i2c->pdata->cfg_gpio)
+
+ if (i2c->pdata->cfg_gpio) {
i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
- else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
+ } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) {
return -EINVAL;
+ }
/* initialise the i2c controller */
- ret = clk_prepare_enable(i2c->clk);
- if (ret) {
- dev_err(&pdev->dev, "I2C clock enable failed\n");
- return ret;
- }
+ clk_prepare_enable(i2c->clk);
ret = s3c24xx_i2c_init(i2c);
clk_disable(i2c->clk);
if (ret != 0) {
dev_err(&pdev->dev, "I2C controller init failed\n");
- clk_unprepare(i2c->clk);
return ret;
}
-
- /*
- * find the IRQ for this unit (note, this relies on the init call to
+ /* find the IRQ for this unit (note, this relies on the init call to
* ensure no current IRQs pending
*/
+
if (!(i2c->quirks & QUIRK_POLL)) {
i2c->irq = ret = platform_get_irq(pdev, 0);
if (ret <= 0) {
return ret;
}
- ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
- 0, dev_name(&pdev->dev), i2c);
+ ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0,
+ dev_name(&pdev->dev), i2c);
+
if (ret != 0) {
dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
clk_unprepare(i2c->clk);
return ret;
}
- /*
- * Note, previous versions of the driver used i2c_add_adapter()
+ /* Note, previous versions of the driver used i2c_add_adapter()
* to add the bus at any number. We now pass the bus number via
* the platform data, so if unset it will now default to always
* being bus 0.
*/
+
i2c->adap.nr = i2c->pdata->bus_num;
i2c->adap.dev.of_node = pdev->dev.of_node;
ret = i2c_add_numbered_adapter(&i2c->adap);
if (ret < 0) {
+ dev_err(&pdev->dev, "failed to add bus to i2c core\n");
pm_runtime_disable(&pdev->dev);
s3c24xx_i2c_deregister_cpufreq(i2c);
clk_unprepare(i2c->clk);
return ret;
}
+ pm_runtime_enable(&i2c->adap.dev);
+
dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
return 0;
}
+/* s3c24xx_i2c_remove
+ *
+ * called when device is removed from the bus
+*/
+
static int s3c24xx_i2c_remove(struct platform_device *pdev)
{
struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
clk_unprepare(i2c->clk);
+ pm_runtime_disable(&i2c->adap.dev);
pm_runtime_disable(&pdev->dev);
s3c24xx_i2c_deregister_cpufreq(i2c);
#ifdef CONFIG_PM
static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
- SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,
- s3c24xx_i2c_resume_noirq)
+#ifdef CONFIG_PM_SLEEP
+ .suspend_noirq = s3c24xx_i2c_suspend_noirq,
+ .resume_noirq = s3c24xx_i2c_resume_noirq,
+ .freeze_noirq = s3c24xx_i2c_suspend_noirq,
+ .thaw_noirq = s3c24xx_i2c_resume_noirq,
+ .poweroff_noirq = s3c24xx_i2c_suspend_noirq,
+ .restore_noirq = s3c24xx_i2c_resume_noirq,
+#endif
};
#define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
#define S3C24XX_DEV_PM_OPS NULL
#endif
+/* device driver for platform bus bits */
+
static struct platform_driver s3c24xx_i2c_driver = {
.probe = s3c24xx_i2c_probe,
.remove = s3c24xx_i2c_remove,
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff