clk: si5351: fix .recalc_rate for multisynth 6-7

MS6 and MS7 do not have the MSx_P3 field. Do the 'params.p3 == 0'
check for MS0-M5 only. See [AN619, p. 6] for details.

Referenced document:
[AN619] Manually Generating an Si5351 Register Map, Rev. 0.4

Signed-off-by: Sergej Sawazki <ce3a@gmx.de>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 48c5298b6bb178e6a12f9022f2fe9d0980635541..e39e1e680b3c6c09b117e7a32a35b7d1a808bf37 100644 (file)
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -607,9 +607,6 @@ static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
        if (!hwdata->params.valid)
                si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
 
-       if (hwdata->params.p3 == 0)
-               return parent_rate;
-
        /*
         * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3)
         * multisync6-7: fOUT = fIN / P1
@@ -617,6 +614,8 @@ static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
        rate = parent_rate;
        if (hwdata->num > 5) {
                m = hwdata->params.p1;
+       } else if (hwdata->params.p3 == 0) {
+               return parent_rate;
        } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) &
                    SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) {
                m = 4;