ixgbe: DCB, X540 devices do not respond to pause frames

DCB enabled X540 devices are not responding to pause frames
due to a missing register set that was added for these
devices that did not exist in other devices.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c
index 865ddd82b268d68bd6c4ef510bf760e0cb514c7e..d50cf78c234d57f634900264191f23bfff7b7a17 100644 (file)
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c
@@ -301,12 +301,17 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en)
                IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
                /*
                 * Enable Receive PFC
-                * We will always honor XOFF frames we receive when
-                * we are in PFC mode.
+                * 82599 will always honor XOFF frames we receive when
+                * we are in PFC mode however X540 only honors enabled
+                * traffic classes.
                 */
                reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
                reg &= ~IXGBE_MFLCN_RFCE;
                reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
+
+               if (hw->mac.type == ixgbe_mac_X540)
+                       reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
+
                IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
 
        } else {

diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 7d0b37d2ab7b7e77378af80a943bbb8706eaf003..f5bec9754c001502d0ee79c3d33b480f8f8b2761 100644 (file)
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -1728,6 +1728,8 @@
 #define IXGBE_MFLCN_RPFCE       0x00000004 /* Receive Priority FC Enable */
 #define IXGBE_MFLCN_RFCE        0x00000008 /* Receive FC Enable */
 
+#define IXGBE_MFLCN_RPFCE_SHIFT                 4
+
 /* Multiple Receive Queue Control */
 #define IXGBE_MRQC_RSSEN                 0x00000001  /* RSS Enable */
 #define IXGBE_MRQC_MRQE_MASK                    0xF /* Bits 3:0 */