unsigned char io_state[6];
unsigned char out_state[6];
unsigned char control[2];
- spinlock_t lock;
+ raw_spinlock_t lock;
unsigned base;
unsigned char irq_mask;
};
unsigned long flags;
unsigned control;
- spin_lock_irqsave(&dio48egpio->lock, flags);
+ raw_spin_lock_irqsave(&dio48egpio->lock, flags);
/* Check if configuring Port C */
if (io_port == 2 || io_port == 5) {
control &= ~BIT(7);
outb(control, control_addr);
- spin_unlock_irqrestore(&dio48egpio->lock, flags);
+ raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
return 0;
}
unsigned long flags;
unsigned control;
- spin_lock_irqsave(&dio48egpio->lock, flags);
+ raw_spin_lock_irqsave(&dio48egpio->lock, flags);
/* Check if configuring Port C */
if (io_port == 2 || io_port == 5) {
control &= ~BIT(7);
outb(control, control_addr);
- spin_unlock_irqrestore(&dio48egpio->lock, flags);
+ raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
return 0;
}
unsigned long flags;
unsigned port_state;
- spin_lock_irqsave(&dio48egpio->lock, flags);
+ raw_spin_lock_irqsave(&dio48egpio->lock, flags);
/* ensure that GPIO is set for input */
if (!(dio48egpio->io_state[port] & mask)) {
- spin_unlock_irqrestore(&dio48egpio->lock, flags);
+ raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
return -EINVAL;
}
port_state = inb(dio48egpio->base + in_port);
- spin_unlock_irqrestore(&dio48egpio->lock, flags);
+ raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
return !!(port_state & mask);
}
const unsigned out_port = (port > 2) ? port + 1 : port;
unsigned long flags;
- spin_lock_irqsave(&dio48egpio->lock, flags);
+ raw_spin_lock_irqsave(&dio48egpio->lock, flags);
if (value)
dio48egpio->out_state[port] |= mask;
outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
- spin_unlock_irqrestore(&dio48egpio->lock, flags);
+ raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
}
static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
out_port = (port > 2) ? port + 1 : port;
bitmask = mask[BIT_WORD(i)] & bits[BIT_WORD(i)];
- spin_lock_irqsave(&dio48egpio->lock, flags);
+ raw_spin_lock_irqsave(&dio48egpio->lock, flags);
/* update output state data and set device gpio register */
dio48egpio->out_state[port] &= ~mask[BIT_WORD(i)];
dio48egpio->out_state[port] |= bitmask;
outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
- spin_unlock_irqrestore(&dio48egpio->lock, flags);
+ raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
/* prepare for next gpio register set */
mask[BIT_WORD(i)] >>= gpio_reg_size;
if (offset != 19 && offset != 43)
return;
- spin_lock_irqsave(&dio48egpio->lock, flags);
+ raw_spin_lock_irqsave(&dio48egpio->lock, flags);
if (offset == 19)
dio48egpio->irq_mask &= ~BIT(0);
/* disable interrupts */
inb(dio48egpio->base + 0xB);
- spin_unlock_irqrestore(&dio48egpio->lock, flags);
+ raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
}
static void dio48e_irq_unmask(struct irq_data *data)
if (offset != 19 && offset != 43)
return;
- spin_lock_irqsave(&dio48egpio->lock, flags);
+ raw_spin_lock_irqsave(&dio48egpio->lock, flags);
if (!dio48egpio->irq_mask) {
/* enable interrupts */
else
dio48egpio->irq_mask |= BIT(1);
- spin_unlock_irqrestore(&dio48egpio->lock, flags);
+ raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
}
static int dio48e_irq_set_type(struct irq_data *data, unsigned flow_type)
generic_handle_irq(irq_find_mapping(chip->irqdomain,
19 + gpio*24));
- spin_lock(&dio48egpio->lock);
+ raw_spin_lock(&dio48egpio->lock);
outb(0x00, dio48egpio->base + 0xF);
- spin_unlock(&dio48egpio->lock);
+ raw_spin_unlock(&dio48egpio->lock);
return IRQ_HANDLED;
}
dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple;
dio48egpio->base = base[id];
- spin_lock_init(&dio48egpio->lock);
+ raw_spin_lock_init(&dio48egpio->lock);
err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio);
if (err) {