ARM: dts: Move Arria10 SDRAM as child of ECC Manager

Changes to support ECC Manager as SDRAM IRQ parent by
1) updating IRQ property values to correct child IRQs
2) moving node under ECC Manager.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index a2f82bb5d24997d1c74a5043e38393de0f5710d6..21f6c3ce2c524c8ad7b39a024bce2eb944269303 100644 (file)
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -572,12 +572,6 @@
                        reg = <0xffcfb100 0x80>;
                };
 
-               sdramedac {
-                       compatible = "altr,sdram-edac-a10";
-                       altr,sdr-syscon = <&sdr>;
-                       interrupts = <0 2 4>, <0 0 4>;
-               };
-
                L2: l2-cache@fffff000 {
                        compatible = "arm,pl310-cache";
                        reg = <0xfffff000 0x1000>;
@@ -614,6 +608,13 @@
                        #interrupt-cells = <2>;
                        ranges;
 
+                       sdramedac {
+                               compatible = "altr,sdram-edac-a10";
+                               altr,sdr-syscon = <&sdr>;
+                               interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+                                            <49 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
                        l2-ecc@ffd06010 {
                                compatible = "altr,socfpga-a10-l2-ecc";
                                reg = <0xffd06010 0x4>;