ARM: dts: meson: mark the clock controller also as reset controller

The clock controller provides a few reset lines as well. Add the
corresponding CPU cores.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 6fe6a159e960b9830cd978c3cea9c32e530bee3e..b98d44fde6b60bc9301a3b23cb65f2ccd0d8e64c 100644 (file)
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -168,6 +168,7 @@
 &cbus {
        clkc: clock-controller@4000 {
                #clock-cells = <1>;
+               #reset-cells = <1>;
                compatible = "amlogic,meson8-clkc";
                reg = <0x8000 0x4>, <0x4000 0x460>;
        };

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 8fce13844b0cc65b0789b241a5035308400eadd8..bc278da7df0d93b260eb36d0080b64de2711c592 100644 (file)
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -119,6 +119,7 @@
 &cbus {
        clkc: clock-controller@4000 {
                #clock-cells = <1>;
+               #reset-cells = <1>;
                compatible = "amlogic,meson8b-clkc";
                reg = <0x8000 0x4>, <0x4000 0x460>;
        };