Blackfin arch: dma add some API and cleanup bf54x DMA definition
authorBryan Wu <bryan.wu@analog.com>
Sun, 21 Oct 2007 16:02:14 +0000 (00:02 +0800)
committerBryan Wu <bryan.wu@analog.com>
Sun, 21 Oct 2007 16:02:14 +0000 (00:02 +0800)
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
arch/blackfin/kernel/bfin_dma_5xx.c
arch/blackfin/mach-bf548/dma.c
include/asm-blackfin/dma.h
include/asm-blackfin/mach-bf548/defBF549.h
include/asm-blackfin/mach-bf548/defBF54x_base.h
include/asm-blackfin/mach-bf548/dma.h

index e19164fb4cd1dfe1de064e201643d72416ff6c53..503eef4c7fec26b831476be01e98a532a2a25e96 100644 (file)
@@ -420,6 +420,32 @@ unsigned short get_dma_curr_ycount(unsigned int channel)
 }
 EXPORT_SYMBOL(get_dma_curr_ycount);
 
+unsigned long get_dma_next_desc_ptr(unsigned int channel)
+{
+       BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
+             && channel < MAX_BLACKFIN_DMA_CHANNEL));
+
+       return dma_ch[channel].regs->next_desc_ptr;
+}
+EXPORT_SYMBOL(get_dma_next_desc_ptr);
+
+unsigned long get_dma_curr_desc_ptr(unsigned int channel)
+{
+       BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
+             && channel < MAX_BLACKFIN_DMA_CHANNEL));
+
+       return dma_ch[channel].regs->curr_desc_ptr;
+}
+
+unsigned long get_dma_curr_addr(unsigned int channel)
+{
+       BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
+             && channel < MAX_BLACKFIN_DMA_CHANNEL));
+
+       return dma_ch[channel].regs->curr_addr_ptr;
+}
+EXPORT_SYMBOL(get_dma_curr_addr);
+
 static void *__dma_memcpy(void *dest, const void *src, size_t size)
 {
        int direction;  /* 1 - address decrease, 0 - address increase */
index a8184113be482361b9ddfc039ac51293be7810d4..957bf1366eff249b0de48f5ae3cad877db96cad2 100644 (file)
@@ -64,6 +64,7 @@
        (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
        (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
 };
+EXPORT_SYMBOL(base_addr);
 
 int channel2irq(unsigned int channel)
 {
index b42a531e7a1b9d90497652897e6ca7d4cd104f3f..b469505af3642ef24c55a48bad402dd127a81c6c 100644 (file)
@@ -109,9 +109,7 @@ struct dma_register {
 
        unsigned long curr_desc_ptr;    /* DMA Current Descriptor Pointer
                                           register */
-       unsigned short curr_addr_ptr_lo;        /* DMA Current Address Pointer
-                                                  register */
-       unsigned short curr_addr_ptr_hi;        /* DMA Current Address Pointer
+       unsigned long curr_addr_ptr;    /* DMA Current Address Pointer
                                                   register */
        unsigned short irq_status;      /* DMA irq status register */
        unsigned short dummy6;
@@ -166,6 +164,9 @@ void set_dma_curr_addr(unsigned int channel, unsigned long addr);
 unsigned short get_dma_curr_irqstat(unsigned int channel);
 unsigned short get_dma_curr_xcount(unsigned int channel);
 unsigned short get_dma_curr_ycount(unsigned int channel);
+unsigned long get_dma_next_desc_ptr(unsigned int channel);
+unsigned long get_dma_curr_desc_ptr(unsigned int channel);
+unsigned long get_dma_curr_addr(unsigned int channel);
 
 /* set large DMA mode descriptor */
 void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg);
index 50b3fe55ef0c182137ea6abd11c5c3a2ee5d3d26..4e46d657e50e8ad2c07013b101d4c6c3dd85ab2e 100644 (file)
 
 /* Bit masks for HOST_STATUS */
 
-#define                     READY  0x1        /* DMA Ready */
+#define                 DMA_READY  0x1        /* DMA Ready */
 #define                  FIFOFULL  0x2        /* FIFO Full */
 #define                 FIFOEMPTY  0x4        /* FIFO Empty */
 #define              DMA_COMPLETE  0x8        /* DMA Complete */
index d40db5cc5d5fea87f2caccafe4663fbb6dab438d..1d365c844ffe54889bc3f547e5b38bb3ac6bb50e 100644 (file)
 
 #define                       MFD  0xf000     /* Multi channel Frame Delay */
 #define                      FSDR  0x80       /* Frame Sync to Data Relationship */
-#define                     MCMEM  0x10       /* Multi channel Frame Mode Enable */
+#define                  MCMEN  0x10       /* Multi channel Frame Mode Enable */
 #define                   MCDRXPE  0x8        /* Multi channel DMA Receive Packing */
 #define                   MCDTXPE  0x4        /* Multi channel DMA Transmit Packing */
 #define                     MCCRM  0x3        /* 2X Clock Recovery Mode */
index 14cb10cc24ae587cce7ec774ce57767e8f37cde3..4d97d3aa97cd938f5db367cfd84f28eaa742a3ae 100644 (file)
@@ -70,5 +70,5 @@
 #define MAX_BLACKFIN_DMA_CHANNEL 32
 
 extern int channel2irq(unsigned int channel);
-extern struct dma_register *base_addr[];
+extern struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL];
 #endif