#define ATTR_PCIE_MEM 0xe8
#define ATTR_SCRATCHPAD 0x0
-struct mbus_dram_target_info dove_mbus_dram_info;
-
static inline void __iomem *ddr_map_sc(int i)
{
return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
/*
* Setup MBUS dram target info.
*/
- dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+ orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
for (i = 0, cs = 0; i < 2; i++) {
u32 map = readl(ddr_map_sc(i));
if (map & 1) {
struct mbus_dram_window *w;
- w = &dove_mbus_dram_info.cs[cs++];
+ w = &orion_mbus_dram_info.cs[cs++];
w->cs_index = i;
w->mbus_attr = 0; /* CS address decoding done inside */
/* the DDR controller, no need to */
w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
}
}
- dove_mbus_dram_info.num_cs = cs;
+ orion_mbus_dram_info.num_cs = cs;
}
#include <linux/irq.h>
#include <plat/time.h>
#include <plat/common.h>
+#include <plat/addr-map.h>
#include "common.h"
static int get_tclk(void);
****************************************************************************/
void __init dove_ehci0_init(void)
{
- orion_ehci_init(&dove_mbus_dram_info,
+ orion_ehci_init(&orion_mbus_dram_info,
DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
}
****************************************************************************/
void __init dove_ehci1_init(void)
{
- orion_ehci_1_init(&dove_mbus_dram_info,
+ orion_ehci_1_init(&orion_mbus_dram_info,
DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
}
****************************************************************************/
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
- orion_ge00_init(eth_data, &dove_mbus_dram_info,
+ orion_ge00_init(eth_data, &orion_mbus_dram_info,
DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
0, get_tclk());
}
****************************************************************************/
void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
{
- orion_sata_init(sata_data, &dove_mbus_dram_info,
+ orion_sata_init(sata_data, &orion_mbus_dram_info,
DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
}
****************************************************************************/
void __init dove_xor0_init(void)
{
- orion_xor0_init(&dove_mbus_dram_info,
+ orion_xor0_init(&orion_mbus_dram_info,
DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
}
struct mv_sata_platform_data;
extern struct sys_timer dove_timer;
-extern struct mbus_dram_target_info dove_mbus_dram_info;
/*
* Basic Dove init functions used early by machine-setup.
#include <plat/pcie.h>
#include <mach/irqs.h>
#include <mach/bridge-regs.h>
+#include <plat/addr-map.h>
#include "common.h"
struct pcie_port {
*/
orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
- orion_pcie_setup(pp->base, &dove_mbus_dram_info);
+ orion_pcie_setup(pp->base, &orion_mbus_dram_info);
/*
* IORESOURCE_IO
#define ATTR_PCIE1_MEM 0xd8
#define ATTR_SRAM 0x01
-struct mbus_dram_target_info kirkwood_mbus_dram_info;
-
/*
* Description of the windows needed by the platform code
*/
/*
* Setup MBUS dram target info.
*/
- orion_setup_cpu_mbus_target(&addr_map_cfg, &kirkwood_mbus_dram_info,
- DDR_WINDOW_CPU_BASE);
+ orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
}
#include <plat/orion_nand.h>
#include <plat/common.h>
#include <plat/time.h>
+#include <plat/addr-map.h>
#include "common.h"
/*****************************************************************************
void __init kirkwood_ehci_init(void)
{
kirkwood_clk_ctrl |= CGC_USB0;
- orion_ehci_init(&kirkwood_mbus_dram_info,
+ orion_ehci_init(&orion_mbus_dram_info,
USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
}
{
kirkwood_clk_ctrl |= CGC_GE0;
- orion_ge00_init(eth_data, &kirkwood_mbus_dram_info,
+ orion_ge00_init(eth_data, &orion_mbus_dram_info,
GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
}
kirkwood_clk_ctrl |= CGC_GE1;
- orion_ge01_init(eth_data, &kirkwood_mbus_dram_info,
+ orion_ge01_init(eth_data, &orion_mbus_dram_info,
GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
}
if (sata_data->n_ports > 1)
kirkwood_clk_ctrl |= CGC_SATA1;
- orion_sata_init(sata_data, &kirkwood_mbus_dram_info,
+ orion_sata_init(sata_data, &orion_mbus_dram_info,
SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
}
mvsdio_data->clock = 100000000;
else
mvsdio_data->clock = 200000000;
- mvsdio_data->dram = &kirkwood_mbus_dram_info;
+ mvsdio_data->dram = &orion_mbus_dram_info;
kirkwood_clk_ctrl |= CGC_SDIO;
kirkwood_sdio.dev.platform_data = mvsdio_data;
platform_device_register(&kirkwood_sdio);
{
kirkwood_clk_ctrl |= CGC_XOR0;
- orion_xor0_init(&kirkwood_mbus_dram_info,
+ orion_xor0_init(&orion_mbus_dram_info,
XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
}
};
static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
- .dram = &kirkwood_mbus_dram_info,
+ .dram = &orion_mbus_dram_info,
.burst = 128,
};
void kirkwood_init_early(void);
void kirkwood_init_irq(void);
-extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
void kirkwood_setup_cpu_mbus(void);
void kirkwood_enable_pcie(void);
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <mach/bridge-regs.h>
+#include <plat/addr-map.h>
#include "common.h"
void kirkwood_enable_pcie(void)
*/
orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
- orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
+ orion_pcie_setup(pp->base, &orion_mbus_dram_info);
return 1;
}
#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
-struct mbus_dram_target_info mv78xx0_mbus_dram_info;
-
static void __init __iomem *win_cfg_base(int win)
{
/*
*/
if (mv78xx0_core_index() == 0)
orion_setup_cpu_mbus_target(&addr_map_cfg,
- &mv78xx0_mbus_dram_info,
DDR_WINDOW_CPU0_BASE);
else
orion_setup_cpu_mbus_target(&addr_map_cfg,
- &mv78xx0_mbus_dram_info,
DDR_WINDOW_CPU1_BASE);
}
#include <plat/orion_nand.h>
#include <plat/time.h>
#include <plat/common.h>
+#include <plat/addr-map.h>
#include "common.h"
static int get_tclk(void);
****************************************************************************/
void __init mv78xx0_ehci0_init(void)
{
- orion_ehci_init(&mv78xx0_mbus_dram_info,
+ orion_ehci_init(&orion_mbus_dram_info,
USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
}
****************************************************************************/
void __init mv78xx0_ehci1_init(void)
{
- orion_ehci_1_init(&mv78xx0_mbus_dram_info,
+ orion_ehci_1_init(&orion_mbus_dram_info,
USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
}
****************************************************************************/
void __init mv78xx0_ehci2_init(void)
{
- orion_ehci_2_init(&mv78xx0_mbus_dram_info,
+ orion_ehci_2_init(&orion_mbus_dram_info,
USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
}
****************************************************************************/
void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
- orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info,
+ orion_ge00_init(eth_data, &orion_mbus_dram_info,
GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
IRQ_MV78XX0_GE_ERR, get_tclk());
}
****************************************************************************/
void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
{
- orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info,
+ orion_ge01_init(eth_data, &orion_mbus_dram_info,
GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
NO_IRQ, get_tclk());
}
eth_data->duplex = DUPLEX_FULL;
}
- orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info,
+ orion_ge10_init(eth_data, &orion_mbus_dram_info,
GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
NO_IRQ, get_tclk());
}
eth_data->duplex = DUPLEX_FULL;
}
- orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info,
+ orion_ge11_init(eth_data, &orion_mbus_dram_info,
GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
NO_IRQ, get_tclk());
}
****************************************************************************/
void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
{
- orion_sata_init(sata_data, &mv78xx0_mbus_dram_info,
+ orion_sata_init(sata_data, &orion_mbus_dram_info,
SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
}
void mv78xx0_init_early(void);
void mv78xx0_init_irq(void);
-extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
void mv78xx0_setup_cpu_mbus(void);
void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
int maj, int min);
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
+#include <plat/addr-map.h>
#include "common.h"
struct pcie_port {
* Generic PCIe unit setup.
*/
orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
- orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info);
+ orion_pcie_setup(pp->base, &orion_mbus_dram_info);
sys->resource[0] = &pp->res[0];
sys->resource[1] = &pp->res[1];
#define ATTR_DEV_BOOT 0xf
#define ATTR_SRAM 0x0
-struct mbus_dram_target_info orion5x_mbus_dram_info;
static int __initdata win_alloc_count;
static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
/*
* Setup MBUS dram target info.
*/
- orion_setup_cpu_mbus_target(&addr_map_cfg, &orion5x_mbus_dram_info,
- ORION5X_DDR_WINDOW_CPU_BASE);
+ orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
}
void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
#include <plat/orion_nand.h>
#include <plat/time.h>
#include <plat/common.h>
+#include <plat/addr-map.h>
#include "common.h"
/*****************************************************************************
****************************************************************************/
void __init orion5x_ehci0_init(void)
{
- orion_ehci_init(&orion5x_mbus_dram_info,
+ orion_ehci_init(&orion_mbus_dram_info,
ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
}
****************************************************************************/
void __init orion5x_ehci1_init(void)
{
- orion_ehci_1_init(&orion5x_mbus_dram_info,
+ orion_ehci_1_init(&orion_mbus_dram_info,
ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
}
****************************************************************************/
void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
{
- orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
+ orion_ge00_init(eth_data, &orion_mbus_dram_info,
ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
IRQ_ORION5X_ETH_ERR, orion5x_tclk);
}
****************************************************************************/
void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
{
- orion_sata_init(sata_data, &orion5x_mbus_dram_info,
+ orion_sata_init(sata_data, &orion_mbus_dram_info,
ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
}
****************************************************************************/
void __init orion5x_xor_init(void)
{
- orion_xor0_init(&orion5x_mbus_dram_info,
+ orion_xor0_init(&orion_mbus_dram_info,
ORION5X_XOR_PHYS_BASE,
ORION5X_XOR_PHYS_BASE + 0x200,
IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
* functions to map its interfaces and by the machine-setup to map its on-
* board devices. Details in /mach-orion/addr-map.c
*/
-extern struct mbus_dram_target_info orion5x_mbus_dram_info;
void orion5x_setup_cpu_mbus_bridge(void);
void orion5x_setup_dev_boot_win(u32 base, u32 size);
void orion5x_setup_dev0_win(u32 base, u32 size);
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
+#include <plat/addr-map.h>
#include "common.h"
/*****************************************************************************
/*
* Generic PCIe unit setup.
*/
- orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
+ orion_pcie_setup(PCIE_BASE, &orion_mbus_dram_info);
/*
* Check whether to apply Orion-1/Orion-NAS PCIe config
/*
* Point PCI unit MBUS decode windows to DRAM space.
*/
- orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
+ orion5x_setup_pci_wins(&orion_mbus_dram_info);
/*
* Master + Slave enable
#include <linux/io.h>
#include <plat/addr-map.h>
+struct mbus_dram_target_info orion_mbus_dram_info;
+
/*
* DDR target is the same on all Orion platforms.
*/
* Setup MBUS dram target info.
*/
void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
- struct mbus_dram_target_info *info,
const u32 ddr_window_cpu_base)
{
void __iomem *addr;
int i;
int cs;
- info->mbus_dram_target_id = TARGET_DDR;
+ orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
addr = (void __iomem *)ddr_window_cpu_base;
if (size & 1) {
struct mbus_dram_window *w;
- w = &info->cs[cs++];
+ w = &orion_mbus_dram_info.cs[cs++];
w->cs_index = i;
w->mbus_attr = 0xf & ~(1 << i);
w->base = base & 0xffff0000;
w->size = (size | 0x0000ffff) + 1;
}
}
- info->num_cs = cs;
+ orion_mbus_dram_info.num_cs = cs;
}
#ifndef __PLAT_ADDR_MAP_H
#define __PLAT_ADDR_MAP_H
+extern struct mbus_dram_target_info orion_mbus_dram_info;
+
struct orion_addr_map_cfg {
const int num_wins; /* Total number of windows */
const int remappable_wins;
const u8 attr, const int remap);
void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
- struct mbus_dram_target_info *info,
const u32 ddr_window_cpu_base);
#endif
projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / commitdiff