drm/amdgpu: improve parse_cs handling a bit
authorChristian König <christian.koenig@amd.com>
Wed, 5 Oct 2016 14:49:19 +0000 (16:49 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 25 Oct 2016 18:38:54 +0000 (14:38 -0400)
This way we can use parse_cs and still keep VM mode enabled.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-and-Tested by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

index 04b7aaf770e41a821946cea4321e9e2c8aca701f..cf03f9f01f4027c3571213600acef4edc5694326 100644 (file)
@@ -822,13 +822,14 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 
        /* Only for UVD/VCE VM emulation */
        if (ring->funcs->parse_cs) {
-               p->job->vm = NULL;
                for (i = 0; i < p->job->num_ibs; i++) {
                        r = amdgpu_ring_parse_cs(ring, p, i);
                        if (r)
                                return r;
                }
-       } else {
+       }
+
+       if (p->job->vm) {
                p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
 
                r = amdgpu_bo_vm_update_pte(p, vm);
@@ -917,7 +918,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
                        offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
                        kptr += chunk_ib->va_start - offset;
 
-                       r =  amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib);
+                       r =  amdgpu_ib_get(adev, vm, chunk_ib->ib_bytes, ib);
                        if (r) {
                                DRM_ERROR("Failed to get ib !\n");
                                return r;
@@ -932,9 +933,9 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
                                return r;
                        }
 
-                       ib->gpu_addr = chunk_ib->va_start;
                }
 
+               ib->gpu_addr = chunk_ib->va_start;
                ib->length_dw = chunk_ib->ib_bytes / 4;
                ib->flags = chunk_ib->flags;
                j++;
index d67eadaa91a3c2fea63c6c167c06319435d46c26..1b54cc218b4732f46106806d1615f1d17a1abacf 100644 (file)
@@ -876,6 +876,9 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
        struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
        int r;
 
+       parser->job->vm = NULL;
+       ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
+
        if (ib->length_dw % 16) {
                DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
                          ib->length_dw);
index 2fb469aa850a8edb244e58c367674cece7b57e4b..05a1ea998fd6dcfc7a3166b94b6e53f1ee7da993 100644 (file)
@@ -642,6 +642,9 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
        uint32_t *size = &tmp;
        int i, r, idx = 0;
 
+       p->job->vm = NULL;
+       ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
+
        r = amdgpu_cs_sysvm_access_required(p);
        if (r)
                return r;