drm/i915/skl: Add WAC6entrylatency

This workaround is for fbc working with rc6 on skylake. Bspec
states that setting this bit needs to be coordinated with uncore
but offers no further details.

v2: rebase

References: HSD#4712857
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-18-git-send-email-mika.kuoppala@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 11e10a0ccd37367d761aa198c5824484926612cf..e8cf7a93f33ffcc9a46e003eb8d32f64e2fa8e63 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2167,6 +2167,9 @@ enum skl_disp_power_wells {
 
 #define FBC_LL_SIZE            (1536)
 
+#define FBC_LLC_READ_CTRL      _MMIO(0x9044)
+#define   FBC_LLC_FULLY_OPEN   (1<<30)
+
 /* Framebuffer compression for GM45+ */
 #define DPFC_CB_BASE           _MMIO(0x3200)
 #define DPFC_CONTROL           _MMIO(0x3208)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index afa5eeed5859bc7dcb3ec24f89bfcb36fb3f4b3c..d8eb23f0ccbf7be155de92a072cbccba2a8206af 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6992,7 +6992,13 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
 
 static void skylake_init_clock_gating(struct drm_device *dev)
 {
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
        gen9_init_clock_gating(dev);
+
+       /* WAC6entrylatency:skl */
+       I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
+                  FBC_LLC_FULLY_OPEN);
 }
 
 static void broadwell_init_clock_gating(struct drm_device *dev)