ARM: tegra: Fix Beaver's PCIe lane configuration

Beaver's PCIe lane configuration most closely matches x2 x2 x2 rather
than x4 x1 x1, since clocks 0 and 2 are used, and lanes 0 and 5 are used,
and the only way those align is with a x2 x2 x2 configuration.

Also, disable root port 1; there's nothing connected to it. Root port 0
is the on-board PCIe Ethernet, and port 2 is the mini-PCIe slot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 21660da2ec5969bd803f78e84270637d0588a66c..51a0ee7b0c85bed62f4772e4a49bd8a8b46ebf80 100644 (file)
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -18,16 +18,16 @@
 
                pci@1,0 {
                        status = "okay";
-                       nvidia,num-lanes = <4>;
+                       nvidia,num-lanes = <2>;
                };
 
                pci@2,0 {
-                       status = "okay";
-                       nvidia,num-lanes = <1>;
+                       nvidia,num-lanes = <2>;
                };
 
                pci@3,0 {
-                       nvidia,num-lanes = <1>;
+                       status = "okay";
+                       nvidia,num-lanes = <2>;
                };
        };