clk: ux500: Register rng clock lookups for u8500

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 4ec6f60e3725ce8416d03b6624152c4b450cb705..87d625b08faf27291c61c2b56899fdf6b043c454 100644 (file)
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -378,6 +378,7 @@ void u8500_clk_init(void)
 
        clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE,
                                BIT(0), 0);
+       clk_register_clkdev(clk, "apb_pclk", "rng");
 
        clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE,
                                BIT(1), 0);
@@ -518,5 +519,5 @@ void u8500_clk_init(void)
        /* Periph6 */
        clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
                        U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE);
-
+       clk_register_clkdev(clk, NULL, "rng");
 }