return hw->phy.ops.reset(hw);
}
-static inline s32 e1000_check_reset_block(struct e1000_hw *hw)
-{
- return hw->phy.ops.check_reset_block(hw);
-}
-
static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
{
return hw->phy.ops.read_reg(hw, offset, data);
* When SoL/IDER sessions are active, autoneg/speed/duplex
* cannot be changed
*/
- if (e1000_check_reset_block(hw)) {
+ if (hw->phy.ops.check_reset_block(hw)) {
e_err("Cannot change link characteristics when SoL/IDER is "
"active.\n");
return -EINVAL;
static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data)
{
+ struct e1000_hw *hw = &adapter->hw;
+
/*
* PHY loopback cannot be performed if SoL/IDER
* sessions are active
*/
- if (e1000_check_reset_block(&adapter->hw)) {
+ if (hw->phy.ops.check_reset_block(hw)) {
e_err("Cannot do PHY loopback test when SoL/IDER is active.\n");
*data = 0;
goto out;
phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
- if (!e1000_check_reset_block(hw)) {
+ if (!hw->phy.ops.check_reset_block(hw)) {
u32 fwsm = er32(FWSM);
/*
oem_reg |= HV_OEM_BITS_LPLU;
/* Set Restart auto-neg to activate the bits */
- if (!e1000_check_reset_block(hw))
+ if (!hw->phy.ops.check_reset_block(hw))
oem_reg |= HV_OEM_BITS_RESTART_AN;
} else {
if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
s32 ret_val = 0;
u16 reg;
- if (e1000_check_reset_block(hw))
+ if (hw->phy.ops.check_reset_block(hw))
return 0;
/* Allow time for h/w to get to quiescent state after reset */
else
oem_reg &= ~HV_OEM_BITS_LPLU;
- if (!e1000_check_reset_block(hw))
+ if (!hw->phy.ops.check_reset_block(hw))
oem_reg |= HV_OEM_BITS_RESTART_AN;
return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
ctrl = er32(CTRL);
- if (!e1000_check_reset_block(hw)) {
+ if (!hw->phy.ops.check_reset_block(hw)) {
/*
* Full-chip reset requires MAC and PHY reset at the same
* time to make sure the interface between MAC and the
{
s32 ret_val;
- if (e1000_check_reset_block(hw))
+ if (hw->phy.ops.check_reset_block(hw))
return 0;
/*
u16 phy_id1, phy_id2;
s32 ret_val;
- if ((hw->mac.type != e1000_pch2lan) || e1000_check_reset_block(hw))
+ if ((hw->mac.type != e1000_pch2lan) ||
+ hw->phy.ops.check_reset_block(hw))
return;
ret_val = hw->phy.ops.acquire(hw);
* In the case of the phy reset being blocked, we already have a link.
* We do not need to set it up again.
*/
- if (e1000_check_reset_block(hw))
+ if (hw->phy.ops.check_reset_block(hw))
return 0;
/*
adapter->hw.phy.ms_type = e1000_ms_hw_default;
}
- if (e1000_check_reset_block(&adapter->hw))
+ if (hw->phy.ops.check_reset_block(hw))
e_info("PHY reset is blocked due to SOL/IDER session.\n");
/* Set initial default active device features */
if (!(adapter->flags & FLAG_HAS_AMT))
e1000e_release_hw_control(adapter);
err_eeprom:
- if (!e1000_check_reset_block(&adapter->hw))
+ if (!hw->phy.ops.check_reset_block(hw))
e1000_phy_hw_reset(&adapter->hw);
err_hw_init:
kfree(adapter->tx_ring);
s32 ret_val;
u32 ctrl;
- ret_val = e1000_check_reset_block(hw);
+ ret_val = phy->ops.check_reset_block(hw);
if (ret_val)
return 0;