arm/tegra: implement support for tegra30

Add support for tegra30 SoC. This includes a device tree compatible type for
this SoC ("nvidia,tegra30") and adds L2 cache initialization for this new SoC.
The clock framework is still missing, which prevents most drivers from working.
The basic IRQs are the same, so remove the dependency on
CONFIG_ARCH_TEGRA_2x_SOC.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Colin Cross <ccross@android.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 996828d68dc0fd3906e8ee829b5dde0e0d41a4b6..b3d78fcd4beffc8be15a7ca571d9cadf1ddce9ce 100644 (file)
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -2,11 +2,8 @@ if ARCH_TEGRA
 
 comment "NVIDIA Tegra options"
 
-choice
-       prompt "Select Tegra processor family for target system"
-
 config ARCH_TEGRA_2x_SOC
-       bool "Tegra 2 family"
+       bool "Enable support for Tegra20 family"
        select CPU_V7
        select ARM_GIC
        select ARCH_REQUIRE_GPIOLIB
@@ -17,7 +14,18 @@ config ARCH_TEGRA_2x_SOC
          Support for NVIDIA Tegra AP20 and T20 processors, based on the
          ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
 
-endchoice
+config ARCH_TEGRA_3x_SOC
+       bool "Enable support for Tegra30 family"
+       select CPU_V7
+       select ARM_GIC
+       select ARCH_REQUIRE_GPIOLIB
+       select USB_ARCH_HAS_EHCI if USB_SUPPORT
+       select USB_ULPI if USB_SUPPORT
+       select USB_ULPI_VIEWPORT if USB_SUPPORT
+       select USE_OF
+       help
+         Support for NVIDIA Tegra T30 processor family, based on the
+         ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
 
 config TEGRA_PCI
        bool "PCI Express support"

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index ced566e5cc14b2e5ea92d832a0f0f148bdaedda5..d9bf7c19660e03517b7d36527674ea514ac0a827 100644 (file)
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)                += tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)                += pinmux-tegra20-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)                += pinmux-tegra30-tables.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)                += board-dt-tegra30.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_SYSTEM_DMA)         += dma.o

diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
new file mode 100644 (file)
index 0000000..f44a29c
--- /dev/null
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -0,0 +1,62 @@
+/*
+ * arch/arm/mach-tegra/board-dt-tegra30.c
+ *
+ * NVIDIA Tegra30 device tree board support
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ * Derived from:
+ *
+ * arch/arm/mach-tegra/board-dt-tegra20.c
+ *
+ * Copyright (C) 2010 Secret Lab Technologies, Ltd.
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include "board.h"
+
+static struct of_device_id tegra_dt_match_table[] __initdata = {
+       { .compatible = "simple-bus", },
+       {}
+};
+
+static void __init tegra30_dt_init(void)
+{
+       of_platform_populate(NULL, tegra_dt_match_table,
+                               NULL, NULL);
+}
+
+static const char *tegra30_dt_board_compat[] = {
+       NULL
+};
+
+DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
+       .map_io         = tegra_map_common_io,
+       .init_early     = tegra30_init_early,
+       .init_irq       = tegra_dt_init_irq,
+       .handle_irq     = gic_handle_irq,
+       .timer          = &tegra_timer,
+       .init_machine   = tegra30_dt_init,
+       .restart        = tegra_assert_system_reset,
+       .dt_compat      = tegra30_dt_board_compat,
+MACHINE_END

diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index fdec3ffa4455a0f39779cc30eee62bcb2f00d8db..628f5a8a0d9aba88b51c6712c567017c2fa90dfd 100644 (file)
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -26,6 +26,7 @@
 void tegra_assert_system_reset(char mode, const char *cmd);
 
 void __init tegra20_init_early(void);
+void __init tegra30_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
 void __init tegra_dt_init_irq(void);

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index a5c14dc304d188d2f69e2570be61755080f350a4..8911e620c092b06d2d2ec35f586705610b28bb7d 100644 (file)
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -102,3 +102,9 @@ void __init tegra20_init_early(void)
        tegra_init_cache(0x331, 0x441);
 }
 #endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+void __init tegra30_init_early(void)
+{
+       tegra_init_cache(0x441, 0x551);
+}
+#endif

diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index 73265af4dda3a607f6af93c8c844a9d0b262b10d..a2146cd6867dc2656791451fbef49fef6992b935 100644 (file)
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -25,7 +25,6 @@
 
 #define IRQ_LOCALTIMER                  29
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
 /* Primary Interrupt Controller */
 #define INT_PRI_BASE                   (INT_GIC_BASE + 32)
 #define INT_TMR1                       (INT_PRI_BASE + 0)
@@ -178,6 +177,5 @@
 #define NR_BOARD_IRQS                  32
 
 #define NR_IRQS                                (INT_BOARD_BASE + NR_BOARD_IRQS)
-#endif
 
 #endif