/**
* struct variant_data - MMCI variant-specific quirks
* @clkreg: default value for MCICLOCK register
+ * @clkreg_enable: enable value for MMCICLOCK register
*/
struct variant_data {
unsigned int clkreg;
+ unsigned int clkreg_enable;
};
static struct variant_data variant_arm = {
};
static struct variant_data variant_u300 = {
+ .clkreg_enable = 1 << 13, /* HWFCEN */
};
static struct variant_data variant_ux500 = {
.clkreg = MCI_CLK_ENABLE,
+ .clkreg_enable = 1 << 14, /* HWFCEN */
};
/*
* This must be called with host->lock held
clk = 255;
host->cclk = host->mclk / (2 * (clk + 1));
}
- if (host->hw_designer == AMBA_VENDOR_ST)
- clk |= MCI_ST_FCEN; /* Bug fix in ST IP block */
+
+ clk |= variant->clkreg_enable;
clk |= MCI_CLK_ENABLE;
/* This hasn't proven to be worthwhile */
/* clk |= MCI_CLK_PWRSAVE; */
#define MCI_4BIT_BUS (1 << 11)
/* 8bit wide buses supported in ST Micro versions */
#define MCI_ST_8BIT_BUS (1 << 12)
-/* HW flow control on the ST Micro version */
-#define MCI_ST_FCEN (1 << 13)
#define MMCIARGUMENT 0x008
#define MMCICOMMAND 0x00c