ath9k_hw: clean up register write buffering
authorFelix Fietkau <nbd@openwrt.org>
Tue, 5 Oct 2010 10:03:42 +0000 (12:03 +0200)
committerJohn W. Linville <linville@tuxdriver.com>
Wed, 6 Oct 2010 20:30:38 +0000 (16:30 -0400)
Throughout the code, DISABLE_REGWRITE_BUFFER is always called right after
REGWRITE_BUFFER_FLUSH. Since that's unlikely to change any time soon, that
makes keeping those ops separate rather pointless, as it only increases
code size and line number counts.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
12 files changed:
drivers/net/wireless/ath/ath.h
drivers/net/wireless/ath/ath9k/ani.c
drivers/net/wireless/ath/ath9k/ar5008_phy.c
drivers/net/wireless/ath/ath9k/ar9002_calib.c
drivers/net/wireless/ath/ath9k/ar9002_hw.c
drivers/net/wireless/ath/ath9k/ar9002_phy.c
drivers/net/wireless/ath/ath9k/calib.c
drivers/net/wireless/ath/ath9k/eeprom_4k.c
drivers/net/wireless/ath/ath9k/htc_drv_init.c
drivers/net/wireless/ath/ath9k/hw.c
drivers/net/wireless/ath/ath9k/hw.h
drivers/net/wireless/ath/ath9k/mac.c

index 5894fcc2c6286085e13763b67e63f1d3ba18699b..cee0191704f513251d083cfdc9a0b78198d5e0c3 100644 (file)
@@ -102,14 +102,12 @@ enum ath_cipher {
  * @read: Register read
  * @write: Register write
  * @enable_write_buffer: Enable multiple register writes
- * @disable_write_buffer: Disable multiple register writes
- * @write_flush: Flush buffered register writes
+ * @write_flush: flush buffered register writes and disable buffering
  */
 struct ath_ops {
        unsigned int (*read)(void *, u32 reg_offset);
        void (*write)(void *, u32 val, u32 reg_offset);
        void (*enable_write_buffer)(void *);
-       void (*disable_write_buffer)(void *);
        void (*write_flush) (void *);
 };
 
index 3fba81e3a61ff3f44c3bcad401bde449ed4fe61c..a1894d2407733596928c63ffcaefe18cf4d9bb04 100644 (file)
@@ -180,7 +180,6 @@ static void ath9k_ani_restart_old(struct ath_hw *ah)
        REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
 
@@ -215,7 +214,6 @@ static void ath9k_ani_restart_new(struct ath_hw *ah)
        REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
 
@@ -643,7 +641,6 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
        REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 }
 
 /*
@@ -737,7 +734,6 @@ static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
        REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 }
 
 static void ath9k_hw_ani_monitor_old(struct ath_hw *ah,
@@ -991,7 +987,6 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
        REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 }
 
 /* Freeze the MIB counters, get the stats and then clear them */
@@ -1261,7 +1256,6 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
        REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        ath9k_enable_mib_counters(ah);
 
index a11ca0247793ef28a2de11afee02c5fe2bf3451d..7b26292daf352adefb6aec42c8849b42221a2daf 100644 (file)
@@ -613,14 +613,11 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
        rx_chainmask = ah->rxchainmask;
        tx_chainmask = ah->txchainmask;
 
-       ENABLE_REGWRITE_BUFFER(ah);
 
        switch (rx_chainmask) {
        case 0x5:
-               DISABLE_REGWRITE_BUFFER(ah);
                REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
                            AR_PHY_SWAP_ALT_CHAIN);
-               ENABLE_REGWRITE_BUFFER(ah);
        case 0x3:
                if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
                        REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
@@ -630,17 +627,18 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
        case 0x1:
        case 0x2:
        case 0x7:
+               ENABLE_REGWRITE_BUFFER(ah);
                REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
                REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
                break;
        default:
+               ENABLE_REGWRITE_BUFFER(ah);
                break;
        }
 
        REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        if (tx_chainmask == 0x5) {
                REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
@@ -726,7 +724,6 @@ static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
        REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 }
 
 
@@ -818,7 +815,6 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
        }
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
                REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
@@ -849,7 +845,6 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
        }
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        if (AR_SREV_9271(ah)) {
                if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
index f0525fb62a2c859fb1c4d07c9c75e2fb078f13e4..15f62cd0cc38a239ceac760e55eff1c9d4c1db92 100644 (file)
@@ -522,7 +522,6 @@ static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
                REG_WRITE(ah, regList[i][0], regList[i][1]);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 }
 
 static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
index fde45082a13b168b88ed25d887c374627f5bfa87..78bdf0cec5f01239dfe9180663de813ed8edf946 100644 (file)
@@ -371,7 +371,6 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
                        REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 
                        REGWRITE_BUFFER_FLUSH(ah);
-                       DISABLE_REGWRITE_BUFFER(ah);
                }
 
                udelay(1000);
@@ -468,7 +467,6 @@ static int ar9002_hw_get_radiorev(struct ath_hw *ah)
                REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
        val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
@@ -627,6 +625,4 @@ void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
        }
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
-
 }
index cd56c86927056038c77906705ea2ae4309437c87..c00cdc67b55ba5291f9ebc758d342f7dfb3184a1 100644 (file)
@@ -415,7 +415,6 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
        REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 }
 
 static void ar9002_olc_init(struct ath_hw *ah)
index 6c38c72915c16ac4a9c14bfbabab6011815a2475..6d509484b5f6144babfc5646412bc0f8d7edaef9 100644 (file)
@@ -300,7 +300,6 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
                }
        }
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 }
 
 
index 872e75b0b574062bd573f48054b74c611906a630..4fa4d8e28c64236ffa5d7547ad5d5234565658bc 100644 (file)
@@ -508,7 +508,6 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
                        }
 
                        REGWRITE_BUFFER_FLUSH(ah);
-                       DISABLE_REGWRITE_BUFFER(ah);
                }
        }
 
@@ -840,7 +839,6 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
        }
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 }
 
 static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
index b100db2766cfc106d0b4f92312873cac2fd22d63..bbb54bc28a44d277ccc274e10feee6195794c610 100644 (file)
@@ -380,15 +380,6 @@ static void ath9k_enable_regwrite_buffer(void *hw_priv)
        atomic_inc(&priv->wmi->mwrite_cnt);
 }
 
-static void ath9k_disable_regwrite_buffer(void *hw_priv)
-{
-       struct ath_hw *ah = (struct ath_hw *) hw_priv;
-       struct ath_common *common = ath9k_hw_common(ah);
-       struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
-
-       atomic_dec(&priv->wmi->mwrite_cnt);
-}
-
 static void ath9k_regwrite_flush(void *hw_priv)
 {
        struct ath_hw *ah = (struct ath_hw *) hw_priv;
@@ -397,6 +388,8 @@ static void ath9k_regwrite_flush(void *hw_priv)
        u32 rsp_status;
        int r;
 
+       atomic_dec(&priv->wmi->mwrite_cnt);
+
        mutex_lock(&priv->wmi->multi_write_mutex);
 
        if (priv->wmi->multi_write_idx) {
@@ -420,7 +413,6 @@ static const struct ath_ops ath9k_common_ops = {
        .read = ath9k_regread,
        .write = ath9k_regwrite,
        .enable_write_buffer = ath9k_enable_regwrite_buffer,
-       .disable_write_buffer = ath9k_disable_regwrite_buffer,
        .write_flush = ath9k_regwrite_flush,
 };
 
index 1b066043d6cb64a7325f95ffc546ddfd8d30e96d..98c97653c21bb184ed48cc179eef5911370c6eeb 100644 (file)
@@ -299,7 +299,6 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
        REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 }
 
 /* This should work for all families including legacy */
@@ -676,7 +675,6 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
        REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 }
 
 static void ath9k_hw_init_pll(struct ath_hw *ah,
@@ -741,7 +739,6 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
        }
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        if (AR_SREV_9300_20_OR_LATER(ah)) {
                REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
@@ -885,7 +882,6 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
        REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        /*
         * Restore TX Trigger Level to its pre-reset value.
@@ -933,7 +929,6 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
        }
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        if (AR_SREV_9300_20_OR_LATER(ah))
                ath9k_hw_reset_txstatus_ring(ah);
@@ -1031,7 +1026,6 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
        REG_WRITE(ah, AR_RTC_RC, rst_flags);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        udelay(50);
 
@@ -1070,7 +1064,6 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
        udelay(2);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        if (!AR_SREV_9300_20_OR_LATER(ah))
                udelay(2);
@@ -1374,7 +1367,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
        REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        r = ath9k_hw_rf_set_freq(ah, chan);
        if (r)
@@ -1386,7 +1378,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        ah->intr_txqs = 0;
        for (i = 0; i < ah->caps.total_queues; i++)
@@ -1434,7 +1425,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
        REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        /*
         * For big endian systems turn on swapping for descriptors
@@ -1684,7 +1674,6 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
        REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        beacon_period &= ~ATH9K_BEACON_ENA;
        if (beacon_period & ATH9K_BEACON_RESET_TSF) {
@@ -1712,7 +1701,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
                  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        REG_RMW_FIELD(ah, AR_RSSI_THR,
                      AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
@@ -1758,7 +1746,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
        REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        REG_SET_BIT(ah, AR_TIMER_MODE,
                    AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
@@ -2176,7 +2163,6 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
                          REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 }
 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
 
index 87dbb850246915f2f78678d8c846d239a9a5d335..d558c51236f9694be9dc8d15830b93a72e1b5f52 100644 (file)
 
 #define ENABLE_REGWRITE_BUFFER(_ah)                                    \
        do {                                                            \
-               if (AR_SREV_9271(_ah))                                  \
+               if (ath9k_hw_common(_ah)->ops->enable_write_buffer)     \
                        ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
        } while (0)
 
-#define DISABLE_REGWRITE_BUFFER(_ah)                                   \
-       do {                                                            \
-               if (AR_SREV_9271(_ah))                                  \
-                       ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
-       } while (0)
-
 #define REGWRITE_BUFFER_FLUSH(_ah)                                     \
        do {                                                            \
-               if (AR_SREV_9271(_ah))                                  \
+               if (ath9k_hw_common(_ah)->ops->write_flush)             \
                        ath9k_hw_common(_ah)->ops->write_flush((_ah));  \
        } while (0)
 
index 3efda8a8a3c1e66e1b0ed71a7a5bbad2a936bb28..e5784595bd0f97d01710790013e7b7bc59394fa7 100644 (file)
@@ -40,7 +40,6 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
        REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 }
 
 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
@@ -530,7 +529,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
        }
 
        REGWRITE_BUFFER_FLUSH(ah);
-       DISABLE_REGWRITE_BUFFER(ah);
 
        if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
                REG_WRITE(ah, AR_DMISC(q),
@@ -553,7 +551,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
                          | AR_D_MISC_POST_FR_BKOFF_DIS);
 
                REGWRITE_BUFFER_FLUSH(ah);
-               DISABLE_REGWRITE_BUFFER(ah);
 
                /*
                 * cwmin and cwmax should be 0 for beacon queue
@@ -585,7 +582,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
                             AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
 
                REGWRITE_BUFFER_FLUSH(ah);
-               DISABLE_REGWRITE_BUFFER(ah);
 
                break;
        case ATH9K_TX_QUEUE_PSPOLL: