.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
};
+static int rsnd_is_accessible_reg(struct rsnd_priv *priv,
+ struct rsnd_gen *gen, enum rsnd_reg reg)
+{
+ if (!gen->regs[reg]) {
+ struct device *dev = rsnd_priv_to_dev(priv);
+
+ dev_err(dev, "unsupported register access %x\n", reg);
+ return 0;
+ }
+
+ return 1;
+}
+
u32 rsnd_read(struct rsnd_priv *priv,
struct rsnd_mod *mod, enum rsnd_reg reg)
{
struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
u32 val;
+ if (!rsnd_is_accessible_reg(priv, gen, reg))
+ return 0;
+
regmap_fields_read(gen->regs[reg], rsnd_mod_id(mod), &val);
return val;
{
struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
+ if (!rsnd_is_accessible_reg(priv, gen, reg))
+ return;
+
regmap_fields_write(gen->regs[reg], rsnd_mod_id(mod), data);
}
{
struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
+ if (!rsnd_is_accessible_reg(priv, gen, reg))
+ return;
+
regmap_fields_update_bits(gen->regs[reg], rsnd_mod_id(mod),
mask, data);
}
}
for (i = 0; i < RSND_REG_MAX; i++) {
+ gen->regs[i] = NULL;
+ if (!regf[i].reg)
+ continue;
+
gen->regs[i] = devm_regmap_field_alloc(dev, gen->regmap, regf[i]);
if (IS_ERR(gen->regs[i]))
return PTR_ERR(gen->regs[i]);