arm: dts: mt2701: Sort DT nodes by register address

This patch rearrange MT2701 DT nodes to keep them in ascending order.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
[mb: fix pio unit address and order]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 7eab6f4c4665746af3a5e7bcaa237d5115d6a428..f3824e7dfa5a690c7c3a53d1dd71cdd416dd300b 100644 (file)
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -96,24 +96,6 @@
                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
        };
 
-       pio: pinctrl@10005000 {
-               compatible = "mediatek,mt2701-pinctrl";
-               reg = <0 0x1000b000 0 0x1000>;
-               mediatek,pctl-regmap = <&syscfg_pctl_a>;
-               pins-are-numbered;
-               gpio-controller;
-               #gpio-cells = <2>;
-               interrupt-controller;
-               #interrupt-cells = <2>;
-               interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-       };
-
-       syscfg_pctl_a: syscfg@10005000 {
-               compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
-               reg = <0 0x10005000 0 0x1000>;
-       };
-
        topckgen: syscon@10000000 {
                compatible = "mediatek,mt2701-topckgen", "syscon";
                reg = <0 0x10000000 0 0x1000>;
@@ -134,6 +116,11 @@
                #reset-cells = <1>;
        };
 
+       syscfg_pctl_a: syscfg@10005000 {
+               compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
+               reg = <0 0x10005000 0 0x1000>;
+       };
+
        watchdog: watchdog@10007000 {
                compatible = "mediatek,mt2701-wdt",
                             "mediatek,mt6589-wdt";
@@ -149,6 +136,19 @@
                clock-names = "system-clk", "rtc-clk";
        };
 
+       pio: pinctrl@1000b000 {
+               compatible = "mediatek,mt2701-pinctrl";
+               reg = <0 0x1000b000 0 0x1000>;
+               mediatek,pctl-regmap = <&syscfg_pctl_a>;
+               pins-are-numbered;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
        sysirq: interrupt-controller@10200100 {
                compatible = "mediatek,mt2701-sysirq",
                             "mediatek,mt6577-sysirq";