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drm/radeon/cik: Add tiling mode index for 1D tiled depth/stencil surfaces
authorMichel Dänzer <michel.daenzer@amd.com>
Wed, 18 Sep 2013 16:23:51 +0000 (18:23 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 20 Sep 2013 21:33:40 +0000 (17:33 -0400)
CIK uses a different index for 1D DST surfaces compared to SI.  Expose
the new index so libdrm_radeon can use it properly for userspace
drivers.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
include/uapi/drm/radeon_drm.h patch | blob | blame | history

diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index fa8b3adf9ffbbc478a7aae0f83ffbe3bd584a91b..46d41e8b0dccec30ec5b52f6dc772bf9e3088dc6 100644 (file)
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -1007,4 +1007,6 @@ struct drm_radeon_info {
 #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA      3
 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA      2
 
+#define CIK_TILE_MODE_DEPTH_STENCIL_1D         5
+
 #endif