clk: qcom: Add GCC_MSS_RESET support
authorAvaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Thu, 15 Dec 2016 12:21:30 +0000 (17:51 +0530)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 10 Jan 2017 00:06:43 +0000 (16:06 -0800)
Add support to use reset control framework for resetting MSS
with hexagon v56 1.5.0.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/qcom/gcc-msm8996.c
include/dt-bindings/clock/qcom,gcc-msm8996.h

index 4b1fc1730d295f0b843cb5cd50de223371dbbb4c..8abc200d4fd36d7b6e87036c9ff6ec9aa908b4c8 100644 (file)
@@ -3448,6 +3448,7 @@ static const struct qcom_reset_map gcc_msm8996_resets[] = {
        [GCC_MSMPU_BCR] = { 0x8d000 },
        [GCC_MSS_Q6_BCR] = { 0x8e000 },
        [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
+       [GCC_MSS_RESTART] = { 0x8f008 },
 };
 
 static const struct regmap_config gcc_msm8996_regmap_config = {
index 1828723eb621225d106622515be190f73540bfea..1f5c42254798e34ac6d6ea56a049f3e0a13dfc49 100644 (file)
 #define GCC_PCIE_PHY_COM_NOCSR_BCR                             102
 #define GCC_USB3_PHY_BCR                                       103
 #define GCC_USB3PHY_PHY_BCR                                    104
+#define GCC_MSS_RESTART                                                105
 
 
 /* Indexes for GDSCs */