x86: Clean up mtrr/amd.c:

Fix trivial style problems :

  ERROR: trailing whitespace
  WARNING: line over 80 characters
  ERROR: do not use C99 // comments

arch/x86/kernel/cpu/mtrr/amd.o:

   text	   data	    bss	    dec	    hex	filename
    501	     32	      0	    533	    215	amd.o.before
    501	     32	      0	    533	    215	amd.o.after

md5:
   62f795eb840ee2d17b03df89e789e76c  amd.o.before.asm
   62f795eb840ee2d17b03df89e789e76c  amd.o.after.asm

Suggested-by: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Yinghai Lu <yinghai@kernel.org>
LKML-Reference: <20090703164225.GA21447@elte.hu>
[ Also restructured comments to be standard, removed stray return,
  converted function description to DocBook style, etc. ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/x86/kernel/cpu/mtrr/amd.c b/arch/x86/kernel/cpu/mtrr/amd.c
index ee2331b0e58fe1b19c6fd22ca6e01cc290b7eb23..33af14110dfdde4d3af4a01fb4bbdc2c2055d162 100644 (file)
--- a/arch/x86/kernel/cpu/mtrr/amd.c
+++ b/arch/x86/kernel/cpu/mtrr/amd.c
@@ -7,15 +7,15 @@
 
 static void
 amd_get_mtrr(unsigned int reg, unsigned long *base,
-            unsigned long *size, mtrr_type * type)
+            unsigned long *size, mtrr_type *type)
 {
        unsigned long low, high;
 
        rdmsr(MSR_K6_UWCCR, low, high);
-       /*  Upper dword is region 1, lower is region 0  */
+       /* Upper dword is region 1, lower is region 0 */
        if (reg == 1)
                low = high;
-       /*  The base masks off on the right alignment  */
+       /* The base masks off on the right alignment */
        *base = (low & 0xFFFE0000) >> PAGE_SHIFT;
        *type = 0;
        if (low & 1)
@@ -27,74 +27,81 @@ amd_get_mtrr(unsigned int reg, unsigned long *base,
                return;
        }
        /*
-        *  This needs a little explaining. The size is stored as an
-        *  inverted mask of bits of 128K granularity 15 bits long offset
-        *  2 bits
+        * This needs a little explaining. The size is stored as an
+        * inverted mask of bits of 128K granularity 15 bits long offset
+        * 2 bits.
         *
-        *  So to get a size we do invert the mask and add 1 to the lowest
-        *  mask bit (4 as its 2 bits in). This gives us a size we then shift
-        *  to turn into 128K blocks
+        * So to get a size we do invert the mask and add 1 to the lowest
+        * mask bit (4 as its 2 bits in). This gives us a size we then shift
+        * to turn into 128K blocks.
         *
-        *  eg              111 1111 1111 1100      is 512K
+        * eg              111 1111 1111 1100      is 512K
         *
-        *  invert          000 0000 0000 0011
-        *  +1              000 0000 0000 0100
-        *  *128K   ...
+        * invert          000 0000 0000 0011
+        * +1              000 0000 0000 0100
+        * *128K   ...
         */
        low = (~low) & 0x1FFFC;
        *size = (low + 4) << (15 - PAGE_SHIFT);
-       return;
 }
 
-static void amd_set_mtrr(unsigned int reg, unsigned long base,
-                        unsigned long size, mtrr_type type)
-/*  [SUMMARY] Set variable MTRR register on the local CPU.
-    <reg> The register to set.
-    <base> The base address of the region.
-    <size> The size of the region. If this is 0 the region is disabled.
-    <type> The type of the region.
-    [RETURNS] Nothing.
-*/
+/**
+ * amd_set_mtrr - Set variable MTRR register on the local CPU.
+ *
+ * @reg The register to set.
+ * @base The base address of the region.
+ * @size The size of the region. If this is 0 the region is disabled.
+ * @type The type of the region.
+ *
+ * Returns nothing.
+ */
+static void
+amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
 {
        u32 regs[2];
 
        /*
-        *  Low is MTRR0 , High MTRR 1
+        * Low is MTRR0, High MTRR 1
         */
        rdmsr(MSR_K6_UWCCR, regs[0], regs[1]);
        /*
-        *  Blank to disable
+        * Blank to disable
         */
-       if (size == 0)
+       if (size == 0) {
                regs[reg] = 0;
-       else
-               /* Set the register to the base, the type (off by one) and an
-                  inverted bitmask of the size The size is the only odd
-                  bit. We are fed say 512K We invert this and we get 111 1111
-                  1111 1011 but if you subtract one and invert you get the   
-                  desired 111 1111 1111 1100 mask
-
-                  But ~(x - 1) == ~x + 1 == -x. Two's complement rocks!  */
+       } else {
+               /*
+                * Set the register to the base, the type (off by one) and an
+                * inverted bitmask of the size The size is the only odd
+                * bit. We are fed say 512K We invert this and we get 111 1111
+                * 1111 1011 but if you subtract one and invert you get the
+                * desired 111 1111 1111 1100 mask
+                *
+                *  But ~(x - 1) == ~x + 1 == -x. Two's complement rocks!
+                */
                regs[reg] = (-size >> (15 - PAGE_SHIFT) & 0x0001FFFC)
                    | (base << PAGE_SHIFT) | (type + 1);
+       }
 
        /*
-        *  The writeback rule is quite specific. See the manual. Its
-        *  disable local interrupts, write back the cache, set the mtrr
+        * The writeback rule is quite specific. See the manual. Its
+        * disable local interrupts, write back the cache, set the mtrr
         */
        wbinvd();
        wrmsr(MSR_K6_UWCCR, regs[0], regs[1]);
 }
 
-static int amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
+static int
+amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
 {
-       /* Apply the K6 block alignment and size rules
-          In order
-          o Uncached or gathering only
-          o 128K or bigger block
-          o Power of 2 block
-          o base suitably aligned to the power
-       */
+       /*
+        * Apply the K6 block alignment and size rules
+        * In order
+        * o Uncached or gathering only
+        * o 128K or bigger block
+        * o Power of 2 block
+        * o base suitably aligned to the power
+        */
        if (type > MTRR_TYPE_WRCOMB || size < (1 << (17 - PAGE_SHIFT))
            || (size & ~(size - 1)) - size || (base & (size - 1)))
                return -EINVAL;
@@ -115,5 +122,3 @@ int __init amd_init_mtrr(void)
        set_mtrr_ops(&amd_mtrr_ops);
        return 0;
 }
-
-//arch_initcall(amd_mtrr_init);